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wifi: rtw89: add DMA busy checking bits to chip info
8852B has less DMA channels, so its checking bits are different from other chips. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220927062611.30484-4-pkshih@realtek.com
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5 changed files with 21 additions and 8 deletions
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@ -2272,19 +2272,19 @@ static int rtw89_poll_txdma_ch_idle_pcie(struct rtw89_dev *rtwdev)
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{
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{
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const struct rtw89_pci_info *info = rtwdev->pci_info;
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const struct rtw89_pci_info *info = rtwdev->pci_info;
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u32 ret, check, dma_busy;
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u32 ret, check, dma_busy;
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u32 dma_busy1 = info->dma_busy1_reg;
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u32 dma_busy1 = info->dma_busy1.addr;
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u32 dma_busy2 = info->dma_busy2_reg;
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u32 dma_busy2 = info->dma_busy2_reg;
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check = B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY |
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check = info->dma_busy1.mask;
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B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY |
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B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY |
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B_AX_CH9_BUSY | B_AX_CH12_BUSY;
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ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
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ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
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10, 100, false, rtwdev, dma_busy1);
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10, 100, false, rtwdev, dma_busy1);
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (!dma_busy2)
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return 0;
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check = B_AX_CH10_BUSY | B_AX_CH11_BUSY;
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check = B_AX_CH10_BUSY | B_AX_CH11_BUSY;
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ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
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ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
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@ -468,6 +468,13 @@
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#define B_AX_ACH0_BUSY BIT(8)
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#define B_AX_ACH0_BUSY BIT(8)
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#define B_AX_RPQ_BUSY BIT(1)
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#define B_AX_RPQ_BUSY BIT(1)
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#define B_AX_RXQ_BUSY BIT(0)
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#define B_AX_RXQ_BUSY BIT(0)
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#define DMA_BUSY1_CHECK (B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
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B_AX_ACH3_BUSY | B_AX_ACH4_BUSY | B_AX_ACH5_BUSY | \
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B_AX_ACH6_BUSY | B_AX_ACH7_BUSY | B_AX_CH8_BUSY | \
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B_AX_CH9_BUSY | B_AX_CH12_BUSY)
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#define DMA_BUSY1_CHECK_V1 (B_AX_ACH0_BUSY | B_AX_ACH1_BUSY | B_AX_ACH2_BUSY | \
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B_AX_ACH3_BUSY | B_AX_CH8_BUSY | B_AX_CH9_BUSY | \
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B_AX_CH12_BUSY)
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#define R_AX_PCIE_DMA_BUSY2 0x131C
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#define R_AX_PCIE_DMA_BUSY2 0x131C
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#define B_AX_CH11_BUSY BIT(1)
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#define B_AX_CH11_BUSY BIT(1)
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@ -754,7 +761,7 @@ struct rtw89_pci_info {
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u32 txbd_rwptr_clr2_reg;
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u32 txbd_rwptr_clr2_reg;
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struct rtw89_reg_def dma_stop1;
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struct rtw89_reg_def dma_stop1;
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struct rtw89_reg_def dma_stop2;
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struct rtw89_reg_def dma_stop2;
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u32 dma_busy1_reg;
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struct rtw89_reg_def dma_busy1;
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u32 dma_busy2_reg;
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u32 dma_busy2_reg;
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u32 dma_busy3_reg;
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u32 dma_busy3_reg;
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@ -35,7 +35,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = {
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.txbd_rwptr_clr2_reg = R_AX_TXBD_RWPTR_CLR2,
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.txbd_rwptr_clr2_reg = R_AX_TXBD_RWPTR_CLR2,
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.dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK},
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.dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK},
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.dma_stop2 = {R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL},
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.dma_stop2 = {R_AX_PCIE_DMA_STOP2, B_AX_TX_STOP2_ALL},
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.dma_busy1_reg = R_AX_PCIE_DMA_BUSY1,
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.dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK},
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.dma_busy2_reg = R_AX_PCIE_DMA_BUSY2,
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.dma_busy2_reg = R_AX_PCIE_DMA_BUSY2,
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.dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
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.dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
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@ -9,6 +9,12 @@
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#include "reg.h"
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#include "reg.h"
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static const struct rtw89_pci_info rtw8852b_pci_info = {
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static const struct rtw89_pci_info rtw8852b_pci_info = {
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.dma_stop1 = {R_AX_PCIE_DMA_STOP1, B_AX_TX_STOP1_MASK_V1},
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.dma_stop2 = {0},
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.dma_busy1 = {R_AX_PCIE_DMA_BUSY1, DMA_BUSY1_CHECK_V1},
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.dma_busy2_reg = 0,
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.dma_busy3_reg = R_AX_PCIE_DMA_BUSY1,
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.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
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.tx_dma_ch_mask = BIT(RTW89_TXCH_ACH4) | BIT(RTW89_TXCH_ACH5) |
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BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
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BIT(RTW89_TXCH_ACH6) | BIT(RTW89_TXCH_ACH7) |
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BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
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BIT(RTW89_TXCH_CH10) | BIT(RTW89_TXCH_CH11),
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@ -44,7 +44,7 @@ static const struct rtw89_pci_info rtw8852c_pci_info = {
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.txbd_rwptr_clr2_reg = R_AX_TXBD_RWPTR_CLR2_V1,
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.txbd_rwptr_clr2_reg = R_AX_TXBD_RWPTR_CLR2_V1,
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.dma_stop1 = {R_AX_HAXI_DMA_STOP1, B_AX_TX_STOP1_MASK},
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.dma_stop1 = {R_AX_HAXI_DMA_STOP1, B_AX_TX_STOP1_MASK},
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.dma_stop2 = {R_AX_HAXI_DMA_STOP2, B_AX_TX_STOP2_ALL},
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.dma_stop2 = {R_AX_HAXI_DMA_STOP2, B_AX_TX_STOP2_ALL},
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.dma_busy1_reg = R_AX_HAXI_DMA_BUSY1,
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.dma_busy1 = {R_AX_HAXI_DMA_BUSY1, DMA_BUSY1_CHECK},
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.dma_busy2_reg = R_AX_HAXI_DMA_BUSY2,
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.dma_busy2_reg = R_AX_HAXI_DMA_BUSY2,
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.dma_busy3_reg = R_AX_HAXI_DMA_BUSY3,
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.dma_busy3_reg = R_AX_HAXI_DMA_BUSY3,
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