mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-04 01:49:36 +00:00
i.MX fixes for 5.0, 3rd round:
It contains a fix for i.MX8MQ EVK board device tree, which makes the broken eMMC support work as expected. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJcVkZzAAoJEFBXWFqHsHzOjfwIALX4Sy/lU2X7M/ISKHwEIYP+ aRQ8ymXjRldTmCQusQVez8wRnphVqFI0Iyk6ktt/xzktmCCrhPDoUSKJWpwOuXj7 xTj5Rn13xNmanZ0Lox1d7w4dLEhWzYM+n2IAQT0UkcwQ6zhZQ+jx8dSbFVr15cd7 grlv5/a98IU7RvpdZzzIJvfHhey4R0diZicE6Gwha94JDGZkeyovdJ+5LvCiU7QU lx632vsnIMWSlqNWmdKK8SvtduhRz099nhp+sZFrP/7CK8E+j1c6nV0rF2onUmkO kvRLpw/IbBheQb9lBmcTrlf6f6Om03juy0Q682bX78qcMLvIAMczNsJNpfrNl8o= =2/kD -----END PGP SIGNATURE----- Merge tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes i.MX fixes for 5.0, 3rd round: It contains a fix for i.MX8MQ EVK board device tree, which makes the broken eMMC support work as expected. * tag 'imx-fixes-5.0-3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8mq: Fix boot from eMMC
This commit is contained in:
commit
62a23bb006
2 changed files with 24 additions and 22 deletions
|
@ -227,34 +227,34 @@ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
|
|
@ -360,6 +360,8 @@ usdhc1: mmc@30b40000 {
|
|||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
bus-width = <4>;
|
||||
|
|
Loading…
Reference in a new issue