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platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read

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To maintain the uniformity in accessing GCR registers, this patch
modifies the S0ix counter read function to use GCR address base
instead of ipc address base.

Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Tested-by: Shanth Murthy <shanth.murthy@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
This commit is contained in:
Kuppuswamy Sathyanarayanan 2017-04-09 15:00:21 -07:00 committed by Andy Shevchenko
parent 9d855d468d
commit 62a7b9c859
2 changed files with 5 additions and 7 deletions
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2
arch/x86/include/asm/intel_pmc_ipc.h
View file

@ -25,6 +25,8 @@
/* GCR reg offsets from gcr base*/
#define PMC_GCR_PMC_CFG_REG 0x08
#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)

10
drivers/platform/x86/intel_pmc_ipc.c
View file

@ -57,10 +57,6 @@
#define IPC_WRITE_BUFFER 0x80
#define IPC_READ_BUFFER 0x90
/* PMC Global Control Registers */
#define GCR_TELEM_DEEP_S0IX_OFFSET 0x1078
#define GCR_TELEM_SHLW_S0IX_OFFSET 0x1080
/* Residency with clock rate at 19.2MHz to usecs */
#define S0IX_RESIDENCY_IN_USECS(d, s) \
({ \
@ -202,7 +198,7 @@ static inline u32 ipc_data_readl(u32 offset)
static inline u64 gcr_data_readq(u32 offset)
{
return readq(ipcdev.ipc_base + offset);
return readq(ipcdev.gcr_mem_base + offset);
}
static inline int is_gcr_valid(u32 offset)
@ -902,8 +898,8 @@ int intel_pmc_s0ix_counter_read(u64 *data)
if (!ipcdev.has_gcr_regs)
return -EACCES;
deep = gcr_data_readq(GCR_TELEM_DEEP_S0IX_OFFSET);
shlw = gcr_data_readq(GCR_TELEM_SHLW_S0IX_OFFSET);
deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG);
shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG);
*data = S0IX_RESIDENCY_IN_USECS(deep, shlw);