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ASoC: max98090: Simplify max98090_readable_register implementation
The readable registers are in consecutive ranges: 0x01 ~ 0x03, 0x0D ~ 0xD1, 0xFF So simplify the implementation by specifying a range of consecutive values in a single case label. Signed-off-by: Axel Lin <axel.lin@ingics.com> Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 2 additions and 69 deletions
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@ -267,75 +267,8 @@ static bool max98090_volatile_register(struct device *dev, unsigned int reg)
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static bool max98090_readable_register(struct device *dev, unsigned int reg)
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static bool max98090_readable_register(struct device *dev, unsigned int reg)
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{
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{
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switch (reg) {
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switch (reg) {
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case M98090_REG_DEVICE_STATUS:
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case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
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case M98090_REG_JACK_STATUS:
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case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
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case M98090_REG_INTERRUPT_S:
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case M98090_REG_RESERVED:
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case M98090_REG_LINE_INPUT_CONFIG:
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case M98090_REG_LINE_INPUT_LEVEL:
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case M98090_REG_INPUT_MODE:
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case M98090_REG_MIC1_INPUT_LEVEL:
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case M98090_REG_MIC2_INPUT_LEVEL:
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case M98090_REG_MIC_BIAS_VOLTAGE:
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case M98090_REG_DIGITAL_MIC_ENABLE:
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case M98090_REG_DIGITAL_MIC_CONFIG:
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case M98090_REG_LEFT_ADC_MIXER:
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case M98090_REG_RIGHT_ADC_MIXER:
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case M98090_REG_LEFT_ADC_LEVEL:
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case M98090_REG_RIGHT_ADC_LEVEL:
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case M98090_REG_ADC_BIQUAD_LEVEL:
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case M98090_REG_ADC_SIDETONE:
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case M98090_REG_SYSTEM_CLOCK:
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case M98090_REG_CLOCK_MODE:
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case M98090_REG_CLOCK_RATIO_NI_MSB:
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case M98090_REG_CLOCK_RATIO_NI_LSB:
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case M98090_REG_CLOCK_RATIO_MI_MSB:
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case M98090_REG_CLOCK_RATIO_MI_LSB:
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case M98090_REG_MASTER_MODE:
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case M98090_REG_INTERFACE_FORMAT:
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case M98090_REG_TDM_CONTROL:
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case M98090_REG_TDM_FORMAT:
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case M98090_REG_IO_CONFIGURATION:
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case M98090_REG_FILTER_CONFIG:
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case M98090_REG_DAI_PLAYBACK_LEVEL:
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case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
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case M98090_REG_LEFT_HP_MIXER:
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case M98090_REG_RIGHT_HP_MIXER:
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case M98090_REG_HP_CONTROL:
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case M98090_REG_LEFT_HP_VOLUME:
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case M98090_REG_RIGHT_HP_VOLUME:
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case M98090_REG_LEFT_SPK_MIXER:
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case M98090_REG_RIGHT_SPK_MIXER:
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case M98090_REG_SPK_CONTROL:
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case M98090_REG_LEFT_SPK_VOLUME:
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case M98090_REG_RIGHT_SPK_VOLUME:
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case M98090_REG_DRC_TIMING:
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case M98090_REG_DRC_COMPRESSOR:
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case M98090_REG_DRC_EXPANDER:
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case M98090_REG_DRC_GAIN:
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case M98090_REG_RCV_LOUTL_MIXER:
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case M98090_REG_RCV_LOUTL_CONTROL:
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case M98090_REG_RCV_LOUTL_VOLUME:
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case M98090_REG_LOUTR_MIXER:
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case M98090_REG_LOUTR_CONTROL:
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case M98090_REG_LOUTR_VOLUME:
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case M98090_REG_JACK_DETECT:
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case M98090_REG_INPUT_ENABLE:
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case M98090_REG_OUTPUT_ENABLE:
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case M98090_REG_LEVEL_CONTROL:
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case M98090_REG_DSP_FILTER_ENABLE:
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case M98090_REG_BIAS_CONTROL:
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case M98090_REG_DAC_CONTROL:
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case M98090_REG_ADC_CONTROL:
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case M98090_REG_DEVICE_SHUTDOWN:
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case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
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case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
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case M98090_REG_DMIC3_VOLUME:
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case M98090_REG_DMIC4_VOLUME:
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case M98090_REG_DMIC34_BQ_PREATTEN:
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case M98090_REG_RECORD_TDM_SLOT:
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case M98090_REG_SAMPLE_RATE:
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case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
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case M98090_REG_REVISION_ID:
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case M98090_REG_REVISION_ID:
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return true;
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return true;
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default:
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default:
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