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tools headers cpufeatures: Sync with the kernel sources
To pick the changes from:2b12993220
("x86/speculation: Add RSB VM Exit protections")28a99e95f5
("x86/amd: Use IBPB for firmware calls")4ad3278df6
("x86/speculation: Disable RRSBA behavior")26aae8ccbc
("x86/cpu/amd: Enumerate BTC_NO")9756bba284
("x86/speculation: Fill RSB on vmexit for IBRS")3ebc170068
("x86/bugs: Add retbleed=ibpb")2dbb887e87
("x86/entry: Add kernel IBRS implementation")6b80b59b35
("x86/bugs: Report AMD retbleed vulnerability")a149180fbc
("x86: Add magic AMD return-thunk")15e67227c4
("x86: Undo return-thunk damage")a883d624ae
("x86/cpufeatures: Move RETPOLINE flags to word 11")aae99a7c9a
("x86/cpufeatures: Introduce x2AVIC CPUID bit")6f33a9daff
("x86: Fix comment for X86_FEATURE_ZEN")5180218615
("x86/speculation/mmio: Enumerate Processor MMIO Stale Data bug") This only causes these perf files to be rebuilt: CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o And addresses this perf build warning: Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h' diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexandre Chartre <alexandre.chartre@oracle.com> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Borislav Petkov <bp@suse.de> Cc: Daniel Sneddon <daniel.sneddon@linux.intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Josh Poimboeuf <jpoimboe@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Wyes Karny <wyes.karny@amd.com> Link: https://lore.kernel.org/lkml/Yvznmu5oHv0ZDN2w@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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fabe0c61d8
commit
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1 changed files with 4 additions and 2 deletions
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@ -219,7 +219,7 @@
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
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#define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
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#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
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#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
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@ -303,7 +303,7 @@
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#define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */
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#define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */
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#define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */
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#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */
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#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
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@ -354,6 +354,7 @@
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#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
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#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
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#define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
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#define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */
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#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */
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#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */
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@ -457,5 +458,6 @@
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#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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#define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
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#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */
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#define X86_BUG_EIBRS_PBRSB X86_BUG(27) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
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#endif /* _ASM_X86_CPUFEATURES_H */
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