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clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
clk_hw_register_composite it's already exported. Preparation for compilation of rK common clock drivers into modules. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022225.23613-2-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
816e87253d
commit
63207c37ea
2 changed files with 40 additions and 39 deletions
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@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
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unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
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div_ops = &clk_half_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(hw))
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goto err_div;
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return clk;
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return hw->clk;
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err_div:
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kfree(gate);
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err_gate:
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kfree(mux);
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return ERR_PTR(-ENOMEM);
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return ERR_CAST(hw);
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}
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@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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u8 gate_shift, u8 gate_flags, unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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: &clk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_composite;
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(hw)) {
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kfree(div);
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kfree(gate);
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return ERR_CAST(hw);
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}
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return clk;
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err_composite:
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kfree(div);
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return hw->clk;
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err_div:
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kfree(gate);
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err_gate:
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@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
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unsigned long flags, struct rockchip_clk_branch *child,
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spinlock_t *lock)
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{
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struct clk_hw *hw;
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struct rockchip_clk_frac *frac;
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struct clk *clk;
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struct clk_gate *gate = NULL;
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struct clk_fractional_divider *div = NULL;
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const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
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@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
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div->approximation = rockchip_fractional_approximation;
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div_ops = &clk_fractional_divider_ops;
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&div->hw, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags | CLK_SET_RATE_UNGATE);
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if (IS_ERR(clk)) {
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&div->hw, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags | CLK_SET_RATE_UNGATE);
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if (IS_ERR(hw)) {
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kfree(frac);
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return clk;
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return ERR_CAST(hw);
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}
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if (child) {
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@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch(
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mux_clk = clk_register(NULL, &frac_mux->hw);
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if (IS_ERR(mux_clk)) {
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kfree(frac);
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return clk;
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return mux_clk;
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}
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rockchip_clk_add_lookup(ctx, mux_clk, child->id);
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@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch(
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if (frac->mux_frac_idx >= 0) {
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pr_debug("%s: found fractional parent in mux at pos %d\n",
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__func__, frac->mux_frac_idx);
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ret = clk_notifier_register(clk, &frac->clk_nb);
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ret = clk_notifier_register(hw->clk, &frac->clk_nb);
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if (ret)
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, name);
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@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch(
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}
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}
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return clk;
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return hw->clk;
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}
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static struct clk *rockchip_clk_register_factor_branch(const char *name,
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@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
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int gate_offset, u8 gate_shift, u8 gate_flags,
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unsigned long flags, spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_gate *gate = NULL;
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struct clk_fixed_factor *fix = NULL;
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@ -349,16 +347,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
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fix->mult = mult;
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fix->div = div;
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&fix->hw, &clk_fixed_factor_ops,
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&gate->hw, &clk_gate_ops, flags);
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if (IS_ERR(clk)) {
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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NULL, NULL,
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&fix->hw, &clk_fixed_factor_ops,
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&gate->hw, &clk_gate_ops, flags);
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if (IS_ERR(hw)) {
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kfree(fix);
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kfree(gate);
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return ERR_CAST(hw);
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}
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return clk;
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return hw->clk;
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}
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struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
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