drivers: thermal: tsens: Add interrupt support
Depending on the IP version, TSENS supports upper, lower and critical threshold interrupts. We only add support for upper and lower threshold interrupts for now. TSENSv2 has an irq [status|clear|mask] bit tuple for each sensor while earlier versions only have a single bit per sensor to denote status and clear. These differences are handled transparently by the interrupt handler. At each interrupt, we reprogram the new upper and lower threshold in the .set_trip callback. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/7508ba143f144407e5dd546107ddae65c380a76f.1572526427.git.amit.kucheria@linaro.org
This commit is contained in:
Amit Kucheria
Daniel Lezcano
parent
bd93ee3cb4
commit
634e11d5b4
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@ -13,6 +13,31 @@
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#include <linux/regmap.h>
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#include "tsens.h"
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/**
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* struct tsens_irq_data - IRQ status and temperature violations
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* @up_viol: upper threshold violated
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* @up_thresh: upper threshold temperature value
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* @up_irq_mask: mask register for upper threshold irqs
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* @up_irq_clear: clear register for uppper threshold irqs
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* @low_viol: lower threshold violated
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* @low_thresh: lower threshold temperature value
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* @low_irq_mask: mask register for lower threshold irqs
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* @low_irq_clear: clear register for lower threshold irqs
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*
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* Structure containing data about temperature threshold settings and
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* irq status if they were violated.
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*/
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struct tsens_irq_data {
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u32 up_viol;
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int up_thresh;
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u32 up_irq_mask;
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u32 up_irq_clear;
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u32 low_viol;
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int low_thresh;
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u32 low_irq_mask;
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u32 low_irq_clear;
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};
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char *qfprom_read(struct device *dev, const char *cname)
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{
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struct nvmem_cell *cell;
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@ -65,6 +90,14 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *p1,
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}
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}
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static inline u32 degc_to_code(int degc, const struct tsens_sensor *s)
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{
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u64 code = (degc * s->slope + s->offset) / SLOPE_FACTOR;
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pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc);
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return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE);
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}
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static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s)
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{
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int degc, num, den;
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@ -117,6 +150,313 @@ static int tsens_hw_to_mC(struct tsens_sensor *s, int field)
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return sign_extend32(temp, resolution) * 100;
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}
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/**
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* tsens_mC_to_hw - Convert temperature to hardware register value
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* @s: Pointer to sensor struct
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* @temp: temperature in milliCelsius to be programmed to hardware
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*
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* This function outputs the value to be written to hardware in ADC code
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* or deciCelsius depending on IP version.
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*
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* Return: ADC code or temperature in deciCelsius.
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*/
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static int tsens_mC_to_hw(struct tsens_sensor *s, int temp)
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{
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struct tsens_priv *priv = s->priv;
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/* milliC to adc code */
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if (priv->feat->adc)
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return degc_to_code(temp / 1000, s);
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/* milliC to deciC */
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return temp / 100;
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}
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static inline enum tsens_ver tsens_version(struct tsens_priv *priv)
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{
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return priv->feat->ver_major;
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}
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static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
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enum tsens_irq_type irq_type, bool enable)
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{
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u32 index = 0;
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switch (irq_type) {
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case UPPER:
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index = UP_INT_CLEAR_0 + hw_id;
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break;
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case LOWER:
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index = LOW_INT_CLEAR_0 + hw_id;
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break;
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}
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regmap_field_write(priv->rf[index], enable ? 0 : 1);
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}
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static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
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enum tsens_irq_type irq_type, bool enable)
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{
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u32 index_mask = 0, index_clear = 0;
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/*
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* To enable the interrupt flag for a sensor:
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* - clear the mask bit
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* To disable the interrupt flag for a sensor:
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* - Mask further interrupts for this sensor
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* - Write 1 followed by 0 to clear the interrupt
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*/
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switch (irq_type) {
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case UPPER:
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index_mask = UP_INT_MASK_0 + hw_id;
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index_clear = UP_INT_CLEAR_0 + hw_id;
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break;
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case LOWER:
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index_mask = LOW_INT_MASK_0 + hw_id;
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index_clear = LOW_INT_CLEAR_0 + hw_id;
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break;
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}
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if (enable) {
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regmap_field_write(priv->rf[index_mask], 0);
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} else {
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regmap_field_write(priv->rf[index_mask], 1);
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regmap_field_write(priv->rf[index_clear], 1);
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regmap_field_write(priv->rf[index_clear], 0);
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}
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}
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/**
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* tsens_set_interrupt - Set state of an interrupt
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* @priv: Pointer to tsens controller private data
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* @hw_id: Hardware ID aka. sensor number
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* @irq_type: irq_type from enum tsens_irq_type
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* @enable: false = disable, true = enable
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*
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* Call IP-specific function to set state of an interrupt
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*
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* Return: void
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*/
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static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id,
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enum tsens_irq_type irq_type, bool enable)
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{
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dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__,
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irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW",
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enable ? "en" : "dis");
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if (tsens_version(priv) > VER_1_X)
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tsens_set_interrupt_v2(priv, hw_id, irq_type, enable);
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else
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tsens_set_interrupt_v1(priv, hw_id, irq_type, enable);
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}
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/**
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* tsens_threshold_violated - Check if a sensor temperature violated a preset threshold
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* @priv: Pointer to tsens controller private data
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* @hw_id: Hardware ID aka. sensor number
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* @d: Pointer to irq state data
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*
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* Return: 0 if threshold was not violated, 1 if it was violated and negative
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* errno in case of errors
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*/
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static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id,
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struct tsens_irq_data *d)
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{
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int ret;
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ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol);
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if (ret)
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return ret;
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ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol);
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if (ret)
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return ret;
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if (d->up_viol || d->low_viol)
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return 1;
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return 0;
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}
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static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id,
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struct tsens_sensor *s, struct tsens_irq_data *d)
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{
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int ret;
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ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear);
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if (ret)
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return ret;
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ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear);
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if (ret)
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return ret;
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if (tsens_version(priv) > VER_1_X) {
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ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask);
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if (ret)
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return ret;
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ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
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if (ret)
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return ret;
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} else {
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/* No mask register on older TSENS */
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d->up_irq_mask = 0;
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d->low_irq_mask = 0;
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}
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d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id);
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d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id);
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dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u) | clr(%u|%u) | mask(%u|%u)\n",
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hw_id, __func__, (d->up_viol || d->low_viol) ? "(V)" : "",
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d->low_viol, d->up_viol, d->low_irq_clear, d->up_irq_clear,
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d->low_irq_mask, d->up_irq_mask);
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dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d)\n", hw_id, __func__,
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(d->up_viol || d->low_viol) ? "(violation)" : "",
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d->low_thresh, d->up_thresh);
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return 0;
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}
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static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
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{
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if (ver > VER_1_X)
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return mask & (1 << hw_id);
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/* v1, v0.1 don't have a irq mask register */
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return 0;
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}
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/**
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* tsens_irq_thread - Threaded interrupt handler for uplow interrupts
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* @irq: irq number
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* @data: tsens controller private data
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*
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* Check all sensors to find ones that violated their threshold limits. If the
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* temperature is still outside the limits, call thermal_zone_device_update() to
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* update the thresholds, else re-enable the interrupts.
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*
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* The level-triggered interrupt might deassert if the temperature returned to
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* within the threshold limits by the time the handler got scheduled. We
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* consider the irq to have been handled in that case.
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*
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* Return: IRQ_HANDLED
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*/
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irqreturn_t tsens_irq_thread(int irq, void *data)
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{
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struct tsens_priv *priv = data;
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struct tsens_irq_data d;
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bool enable = true, disable = false;
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unsigned long flags;
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int temp, ret, i;
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for (i = 0; i < priv->num_sensors; i++) {
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bool trigger = false;
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struct tsens_sensor *s = &priv->sensor[i];
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u32 hw_id = s->hw_id;
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if (IS_ERR(priv->sensor[i].tzd))
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continue;
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if (!tsens_threshold_violated(priv, hw_id, &d))
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continue;
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ret = get_temp_tsens_valid(s, &temp);
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if (ret) {
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dev_err(priv->dev, "[%u] %s: error reading sensor\n", hw_id, __func__);
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continue;
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}
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spin_lock_irqsave(&priv->ul_lock, flags);
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tsens_read_irq_state(priv, hw_id, s, &d);
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if (d.up_viol &&
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!masked_irq(hw_id, d.up_irq_mask, tsens_version(priv))) {
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tsens_set_interrupt(priv, hw_id, UPPER, disable);
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if (d.up_thresh > temp) {
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dev_dbg(priv->dev, "[%u] %s: re-arm upper\n",
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priv->sensor[i].hw_id, __func__);
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tsens_set_interrupt(priv, hw_id, UPPER, enable);
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} else {
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trigger = true;
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/* Keep irq masked */
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}
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} else if (d.low_viol &&
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!masked_irq(hw_id, d.low_irq_mask, tsens_version(priv))) {
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tsens_set_interrupt(priv, hw_id, LOWER, disable);
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if (d.low_thresh < temp) {
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dev_dbg(priv->dev, "[%u] %s: re-arm low\n",
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priv->sensor[i].hw_id, __func__);
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tsens_set_interrupt(priv, hw_id, LOWER, enable);
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} else {
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trigger = true;
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/* Keep irq masked */
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}
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}
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spin_unlock_irqrestore(&priv->ul_lock, flags);
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if (trigger) {
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dev_dbg(priv->dev, "[%u] %s: TZ update trigger (%d mC)\n",
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hw_id, __func__, temp);
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thermal_zone_device_update(priv->sensor[i].tzd,
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THERMAL_EVENT_UNSPECIFIED);
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} else {
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dev_dbg(priv->dev, "[%u] %s: no violation: %d\n",
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hw_id, __func__, temp);
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}
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}
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return IRQ_HANDLED;
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}
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int tsens_set_trips(void *_sensor, int low, int high)
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{
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struct tsens_sensor *s = _sensor;
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struct tsens_priv *priv = s->priv;
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struct device *dev = priv->dev;
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struct tsens_irq_data d;
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unsigned long flags;
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int high_val, low_val, cl_high, cl_low;
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u32 hw_id = s->hw_id;
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dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
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hw_id, __func__, low, high);
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cl_high = clamp_val(high, -40000, 120000);
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cl_low = clamp_val(low, -40000, 120000);
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high_val = tsens_mC_to_hw(s, cl_high);
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low_val = tsens_mC_to_hw(s, cl_low);
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spin_lock_irqsave(&priv->ul_lock, flags);
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tsens_read_irq_state(priv, hw_id, s, &d);
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/* Write the new thresholds and clear the status */
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regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val);
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regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val);
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tsens_set_interrupt(priv, hw_id, LOWER, true);
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tsens_set_interrupt(priv, hw_id, UPPER, true);
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spin_unlock_irqrestore(&priv->ul_lock, flags);
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dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n",
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s->hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high);
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return 0;
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}
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int tsens_enable_irq(struct tsens_priv *priv)
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{
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int ret;
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int val = tsens_version(priv) > VER_1_X ? 7 : 1;
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ret = regmap_field_write(priv->rf[INT_EN], val);
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if (ret < 0)
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dev_err(priv->dev, "%s: failed to enable interrupts\n", __func__);
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return ret;
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}
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void tsens_disable_irq(struct tsens_priv *priv)
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{
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regmap_field_write(priv->rf[INT_EN], 0);
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}
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int get_temp_tsens_valid(struct tsens_sensor *s, int *temp)
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{
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struct tsens_priv *priv = s->priv;
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@ -187,7 +527,7 @@ static int dbg_version_show(struct seq_file *s, void *data)
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u32 maj_ver, min_ver, step_ver;
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int ret;
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if (tsens_ver(priv) > VER_0_1) {
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if (tsens_version(priv) > VER_0_1) {
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ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver);
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if (ret)
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return ret;
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@ -292,7 +632,7 @@ int __init init_common(struct tsens_priv *priv)
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goto err_put_device;
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}
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if (tsens_ver(priv) > VER_0_1) {
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if (tsens_version(priv) > VER_0_1) {
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for (i = VER_MAJOR; i <= VER_STEP; i++) {
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priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
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priv->fields[i]);
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@ -322,24 +662,29 @@ int __init init_common(struct tsens_priv *priv)
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ret = PTR_ERR(priv->rf[SENSOR_EN]);
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goto err_put_device;
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}
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/* now alloc regmap_fields in tm_map */
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for (i = 0, j = LAST_TEMP_0; i < priv->feat->max_sensors; i++, j++) {
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priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map,
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priv->fields[j]);
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if (IS_ERR(priv->rf[j])) {
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ret = PTR_ERR(priv->rf[j]);
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goto err_put_device;
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}
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priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map,
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priv->fields[INT_EN]);
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if (IS_ERR(priv->rf[INT_EN])) {
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ret = PTR_ERR(priv->rf[INT_EN]);
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goto err_put_device;
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}
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for (i = 0, j = VALID_0; i < priv->feat->max_sensors; i++, j++) {
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priv->rf[j] = devm_regmap_field_alloc(dev, priv->tm_map,
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priv->fields[j]);
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if (IS_ERR(priv->rf[j])) {
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ret = PTR_ERR(priv->rf[j]);
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goto err_put_device;
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/* This loop might need changes if enum regfield_ids is reordered */
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for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
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for (i = 0; i < priv->feat->max_sensors; i++) {
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int idx = j + i;
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priv->rf[idx] = devm_regmap_field_alloc(dev, priv->tm_map,
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priv->fields[idx]);
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if (IS_ERR(priv->rf[idx])) {
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ret = PTR_ERR(priv->rf[idx]);
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goto err_put_device;
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}
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}
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}
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spin_lock_init(&priv->ul_lock);
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tsens_enable_irq(priv);
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tsens_debug_init(op);
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|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -347,9 +347,20 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = {
|
|||
/* INTERRUPT ENABLE */
|
||||
[INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
|
||||
|
||||
/* UPPER/LOWER TEMPERATURE THRESHOLDS */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
|
||||
|
||||
/* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
|
||||
|
||||
/* NO CRITICAL INTERRUPT SUPPORT on v0.1 */
|
||||
|
||||
/* Sn_STATUS */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
|
||||
/* No VALID field on v0.1 */
|
||||
/* xxx_STATUS bits: 1 == threshold violated */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
|
||||
#define TM_Sn_STATUS_OFF 0x0044
|
||||
#define TM_TRDY_OFF 0x0084
|
||||
#define TM_HIGH_LOW_INT_STATUS_OFF 0x0088
|
||||
#define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090
|
||||
|
||||
/* eeprom layout data for qcs404/405 (v1) */
|
||||
#define BASE0_MASK 0x000007f8
|
||||
|
|
@ -168,9 +170,36 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
|
|||
/* INTERRUPT ENABLE */
|
||||
[INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
|
||||
|
||||
/* UPPER/LOWER TEMPERATURE THRESHOLDS */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOW_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 0, 9),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UP_THRESH, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 10, 19),
|
||||
|
||||
/* UPPER/LOWER INTERRUPTS [CLEAR/STATUS] */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOW_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 20, 20),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UP_INT_CLEAR, TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF, 21, 21),
|
||||
[LOW_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 0, 0),
|
||||
[LOW_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 1, 1),
|
||||
[LOW_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 2, 2),
|
||||
[LOW_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 3, 3),
|
||||
[LOW_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 4, 4),
|
||||
[LOW_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 5, 5),
|
||||
[LOW_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 6, 6),
|
||||
[LOW_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 7, 7),
|
||||
[UP_INT_STATUS_0] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 8, 8),
|
||||
[UP_INT_STATUS_1] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 9, 9),
|
||||
[UP_INT_STATUS_2] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 10, 10),
|
||||
[UP_INT_STATUS_3] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 11, 11),
|
||||
[UP_INT_STATUS_4] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 12, 12),
|
||||
[UP_INT_STATUS_5] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 13, 13),
|
||||
[UP_INT_STATUS_6] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 14, 14),
|
||||
[UP_INT_STATUS_7] = REG_FIELD(TM_HIGH_LOW_INT_STATUS_OFF, 15, 15),
|
||||
|
||||
/* NO CRITICAL INTERRUPT SUPPORT on v1 */
|
||||
|
||||
/* Sn_STATUS */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14),
|
||||
/* xxx_STATUS bits: 1 == threshold violated */
|
||||
REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
|
||||
REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
|
||||
|
|
|
|||
|
|
@ -50,9 +50,22 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
|
|||
/* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */
|
||||
[INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 2),
|
||||
|
||||
/* TEMPERATURE THRESHOLDS */
|
||||
REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 0, 11),
|
||||
REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH, TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12, 23),
|
||||
|
||||
/* INTERRUPTS [CLEAR/STATUS/MASK] */
|
||||
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
|
||||
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
|
||||
REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
|
||||
REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS, TM_UPPER_LOWER_INT_STATUS_OFF),
|
||||
REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR, TM_UPPER_LOWER_INT_CLEAR_OFF),
|
||||
REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK, TM_UPPER_LOWER_INT_MASK_OFF),
|
||||
|
||||
/* Sn_STATUS */
|
||||
REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 11),
|
||||
REG_FIELD_FOR_EACH_SENSOR16(VALID, TM_Sn_STATUS_OFF, 21, 21),
|
||||
/* xxx_STATUS bits: 1 == threshold violated */
|
||||
REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS, TM_Sn_STATUS_OFF, 16, 16),
|
||||
REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS, TM_Sn_STATUS_OFF, 17, 17),
|
||||
REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS, TM_Sn_STATUS_OFF, 18, 18),
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -78,12 +79,14 @@ MODULE_DEVICE_TABLE(of, tsens_table);
|
|||
static const struct thermal_zone_of_device_ops tsens_of_ops = {
|
||||
.get_temp = tsens_get_temp,
|
||||
.get_trend = tsens_get_trend,
|
||||
.set_trips = tsens_set_trips,
|
||||
};
|
||||
|
||||
static int tsens_register(struct tsens_priv *priv)
|
||||
{
|
||||
int i;
|
||||
int i, ret, irq;
|
||||
struct thermal_zone_device *tzd;
|
||||
struct platform_device *pdev;
|
||||
|
||||
for (i = 0; i < priv->num_sensors; i++) {
|
||||
priv->sensor[i].priv = priv;
|
||||
|
|
@ -96,7 +99,31 @@ static int tsens_register(struct tsens_priv *priv)
|
|||
if (priv->ops->enable)
|
||||
priv->ops->enable(priv, i);
|
||||
}
|
||||
return 0;
|
||||
|
||||
pdev = of_find_device_by_node(priv->dev->of_node);
|
||||
if (!pdev)
|
||||
return -ENODEV;
|
||||
|
||||
irq = platform_get_irq_byname(pdev, "uplow");
|
||||
if (irq < 0) {
|
||||
ret = irq;
|
||||
goto err_put_device;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, irq,
|
||||
NULL, tsens_irq_thread,
|
||||
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
|
||||
dev_name(&pdev->dev), priv);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: failed to get irq\n", __func__);
|
||||
goto err_put_device;
|
||||
}
|
||||
|
||||
enable_irq_wake(irq);
|
||||
|
||||
err_put_device:
|
||||
put_device(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tsens_probe(struct platform_device *pdev)
|
||||
|
|
@ -178,6 +205,7 @@ static int tsens_remove(struct platform_device *pdev)
|
|||
struct tsens_priv *priv = platform_get_drvdata(pdev);
|
||||
|
||||
debugfs_remove_recursive(priv->debug_root);
|
||||
tsens_disable_irq(priv);
|
||||
if (priv->ops->disable)
|
||||
priv->ops->disable(priv);
|
||||
|
||||
|
|
|
|||
|
|
@ -13,8 +13,10 @@
|
|||
#define CAL_DEGC_PT2 120
|
||||
#define SLOPE_FACTOR 1000
|
||||
#define SLOPE_DEFAULT 3200
|
||||
#define THRESHOLD_MAX_ADC_CODE 0x3ff
|
||||
#define THRESHOLD_MIN_ADC_CODE 0x0
|
||||
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/thermal.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
|
@ -27,6 +29,11 @@ enum tsens_ver {
|
|||
VER_2_X,
|
||||
};
|
||||
|
||||
enum tsens_irq_type {
|
||||
LOWER,
|
||||
UPPER,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tsens_sensor - data for each sensor connected to the tsens device
|
||||
* @priv: tsens device instance that this sensor is connected to
|
||||
|
|
@ -100,22 +107,66 @@ struct tsens_ops {
|
|||
[_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
|
||||
[_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
|
||||
|
||||
/* reg_field IDs to use as an index into an array */
|
||||
#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \
|
||||
[_name##_##0] = REG_FIELD(_offset, 0, 0), \
|
||||
[_name##_##1] = REG_FIELD(_offset, 1, 1), \
|
||||
[_name##_##2] = REG_FIELD(_offset, 2, 2), \
|
||||
[_name##_##3] = REG_FIELD(_offset, 3, 3), \
|
||||
[_name##_##4] = REG_FIELD(_offset, 4, 4), \
|
||||
[_name##_##5] = REG_FIELD(_offset, 5, 5), \
|
||||
[_name##_##6] = REG_FIELD(_offset, 6, 6), \
|
||||
[_name##_##7] = REG_FIELD(_offset, 7, 7), \
|
||||
[_name##_##8] = REG_FIELD(_offset, 8, 8), \
|
||||
[_name##_##9] = REG_FIELD(_offset, 9, 9), \
|
||||
[_name##_##10] = REG_FIELD(_offset, 10, 10), \
|
||||
[_name##_##11] = REG_FIELD(_offset, 11, 11), \
|
||||
[_name##_##12] = REG_FIELD(_offset, 12, 12), \
|
||||
[_name##_##13] = REG_FIELD(_offset, 13, 13), \
|
||||
[_name##_##14] = REG_FIELD(_offset, 14, 14), \
|
||||
[_name##_##15] = REG_FIELD(_offset, 15, 15)
|
||||
|
||||
#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \
|
||||
[_name##_##0] = REG_FIELD(_offset, 16, 16), \
|
||||
[_name##_##1] = REG_FIELD(_offset, 17, 17), \
|
||||
[_name##_##2] = REG_FIELD(_offset, 18, 18), \
|
||||
[_name##_##3] = REG_FIELD(_offset, 19, 19), \
|
||||
[_name##_##4] = REG_FIELD(_offset, 20, 20), \
|
||||
[_name##_##5] = REG_FIELD(_offset, 21, 21), \
|
||||
[_name##_##6] = REG_FIELD(_offset, 22, 22), \
|
||||
[_name##_##7] = REG_FIELD(_offset, 23, 23), \
|
||||
[_name##_##8] = REG_FIELD(_offset, 24, 24), \
|
||||
[_name##_##9] = REG_FIELD(_offset, 25, 25), \
|
||||
[_name##_##10] = REG_FIELD(_offset, 26, 26), \
|
||||
[_name##_##11] = REG_FIELD(_offset, 27, 27), \
|
||||
[_name##_##12] = REG_FIELD(_offset, 28, 28), \
|
||||
[_name##_##13] = REG_FIELD(_offset, 29, 29), \
|
||||
[_name##_##14] = REG_FIELD(_offset, 30, 30), \
|
||||
[_name##_##15] = REG_FIELD(_offset, 31, 31)
|
||||
|
||||
/*
|
||||
* reg_field IDs to use as an index into an array
|
||||
* If you change the order of the entries, check the devm_regmap_field_alloc()
|
||||
* calls in init_common()
|
||||
*/
|
||||
enum regfield_ids {
|
||||
/* ----- SROT ------ */
|
||||
/* HW_VER */
|
||||
VER_MAJOR = 0,
|
||||
VER_MAJOR,
|
||||
VER_MINOR,
|
||||
VER_STEP,
|
||||
/* CTRL_OFFSET */
|
||||
TSENS_EN = 3,
|
||||
TSENS_EN,
|
||||
TSENS_SW_RST,
|
||||
SENSOR_EN,
|
||||
CODE_OR_TEMP,
|
||||
|
||||
/* ----- TM ------ */
|
||||
/* TRDY */
|
||||
TRDY,
|
||||
/* INTERRUPT ENABLE */
|
||||
INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
|
||||
/* STATUS */
|
||||
LAST_TEMP_0 = 7, /* Last temperature reading */
|
||||
LAST_TEMP_0, /* Last temperature reading */
|
||||
LAST_TEMP_1,
|
||||
LAST_TEMP_2,
|
||||
LAST_TEMP_3,
|
||||
|
|
@ -131,7 +182,7 @@ enum regfield_ids {
|
|||
LAST_TEMP_13,
|
||||
LAST_TEMP_14,
|
||||
LAST_TEMP_15,
|
||||
VALID_0 = 23, /* VALID reading or not */
|
||||
VALID_0, /* VALID reading or not */
|
||||
VALID_1,
|
||||
VALID_2,
|
||||
VALID_3,
|
||||
|
|
@ -147,6 +198,182 @@ enum regfield_ids {
|
|||
VALID_13,
|
||||
VALID_14,
|
||||
VALID_15,
|
||||
LOWER_STATUS_0, /* LOWER threshold violated */
|
||||
LOWER_STATUS_1,
|
||||
LOWER_STATUS_2,
|
||||
LOWER_STATUS_3,
|
||||
LOWER_STATUS_4,
|
||||
LOWER_STATUS_5,
|
||||
LOWER_STATUS_6,
|
||||
LOWER_STATUS_7,
|
||||
LOWER_STATUS_8,
|
||||
LOWER_STATUS_9,
|
||||
LOWER_STATUS_10,
|
||||
LOWER_STATUS_11,
|
||||
LOWER_STATUS_12,
|
||||
LOWER_STATUS_13,
|
||||
LOWER_STATUS_14,
|
||||
LOWER_STATUS_15,
|
||||
LOW_INT_STATUS_0, /* LOWER interrupt status */
|
||||
LOW_INT_STATUS_1,
|
||||
LOW_INT_STATUS_2,
|
||||
LOW_INT_STATUS_3,
|
||||
LOW_INT_STATUS_4,
|
||||
LOW_INT_STATUS_5,
|
||||
LOW_INT_STATUS_6,
|
||||
LOW_INT_STATUS_7,
|
||||
LOW_INT_STATUS_8,
|
||||
LOW_INT_STATUS_9,
|
||||
LOW_INT_STATUS_10,
|
||||
LOW_INT_STATUS_11,
|
||||
LOW_INT_STATUS_12,
|
||||
LOW_INT_STATUS_13,
|
||||
LOW_INT_STATUS_14,
|
||||
LOW_INT_STATUS_15,
|
||||
LOW_INT_CLEAR_0, /* LOWER interrupt clear */
|
||||
LOW_INT_CLEAR_1,
|
||||
LOW_INT_CLEAR_2,
|
||||
LOW_INT_CLEAR_3,
|
||||
LOW_INT_CLEAR_4,
|
||||
LOW_INT_CLEAR_5,
|
||||
LOW_INT_CLEAR_6,
|
||||
LOW_INT_CLEAR_7,
|
||||
LOW_INT_CLEAR_8,
|
||||
LOW_INT_CLEAR_9,
|
||||
LOW_INT_CLEAR_10,
|
||||
LOW_INT_CLEAR_11,
|
||||
LOW_INT_CLEAR_12,
|
||||
LOW_INT_CLEAR_13,
|
||||
LOW_INT_CLEAR_14,
|
||||
LOW_INT_CLEAR_15,
|
||||
LOW_INT_MASK_0, /* LOWER interrupt mask */
|
||||
LOW_INT_MASK_1,
|
||||
LOW_INT_MASK_2,
|
||||
LOW_INT_MASK_3,
|
||||
LOW_INT_MASK_4,
|
||||
LOW_INT_MASK_5,
|
||||
LOW_INT_MASK_6,
|
||||
LOW_INT_MASK_7,
|
||||
LOW_INT_MASK_8,
|
||||
LOW_INT_MASK_9,
|
||||
LOW_INT_MASK_10,
|
||||
LOW_INT_MASK_11,
|
||||
LOW_INT_MASK_12,
|
||||
LOW_INT_MASK_13,
|
||||
LOW_INT_MASK_14,
|
||||
LOW_INT_MASK_15,
|
||||
LOW_THRESH_0, /* LOWER threshold values */
|
||||
LOW_THRESH_1,
|
||||
LOW_THRESH_2,
|
||||
LOW_THRESH_3,
|
||||
LOW_THRESH_4,
|
||||
LOW_THRESH_5,
|
||||
LOW_THRESH_6,
|
||||
LOW_THRESH_7,
|
||||
LOW_THRESH_8,
|
||||
LOW_THRESH_9,
|
||||
LOW_THRESH_10,
|
||||
LOW_THRESH_11,
|
||||
LOW_THRESH_12,
|
||||
LOW_THRESH_13,
|
||||
LOW_THRESH_14,
|
||||
LOW_THRESH_15,
|
||||
UPPER_STATUS_0, /* UPPER threshold violated */
|
||||
UPPER_STATUS_1,
|
||||
UPPER_STATUS_2,
|
||||
UPPER_STATUS_3,
|
||||
UPPER_STATUS_4,
|
||||
UPPER_STATUS_5,
|
||||
UPPER_STATUS_6,
|
||||
UPPER_STATUS_7,
|
||||
UPPER_STATUS_8,
|
||||
UPPER_STATUS_9,
|
||||
UPPER_STATUS_10,
|
||||
UPPER_STATUS_11,
|
||||
UPPER_STATUS_12,
|
||||
UPPER_STATUS_13,
|
||||
UPPER_STATUS_14,
|
||||
UPPER_STATUS_15,
|
||||
UP_INT_STATUS_0, /* UPPER interrupt status */
|
||||
UP_INT_STATUS_1,
|
||||
UP_INT_STATUS_2,
|
||||
UP_INT_STATUS_3,
|
||||
UP_INT_STATUS_4,
|
||||
UP_INT_STATUS_5,
|
||||
UP_INT_STATUS_6,
|
||||
UP_INT_STATUS_7,
|
||||
UP_INT_STATUS_8,
|
||||
UP_INT_STATUS_9,
|
||||
UP_INT_STATUS_10,
|
||||
UP_INT_STATUS_11,
|
||||
UP_INT_STATUS_12,
|
||||
UP_INT_STATUS_13,
|
||||
UP_INT_STATUS_14,
|
||||
UP_INT_STATUS_15,
|
||||
UP_INT_CLEAR_0, /* UPPER interrupt clear */
|
||||
UP_INT_CLEAR_1,
|
||||
UP_INT_CLEAR_2,
|
||||
UP_INT_CLEAR_3,
|
||||
UP_INT_CLEAR_4,
|
||||
UP_INT_CLEAR_5,
|
||||
UP_INT_CLEAR_6,
|
||||
UP_INT_CLEAR_7,
|
||||
UP_INT_CLEAR_8,
|
||||
UP_INT_CLEAR_9,
|
||||
UP_INT_CLEAR_10,
|
||||
UP_INT_CLEAR_11,
|
||||
UP_INT_CLEAR_12,
|
||||
UP_INT_CLEAR_13,
|
||||
UP_INT_CLEAR_14,
|
||||
UP_INT_CLEAR_15,
|
||||
UP_INT_MASK_0, /* UPPER interrupt mask */
|
||||
UP_INT_MASK_1,
|
||||
UP_INT_MASK_2,
|
||||
UP_INT_MASK_3,
|
||||
UP_INT_MASK_4,
|
||||
UP_INT_MASK_5,
|
||||
UP_INT_MASK_6,
|
||||
UP_INT_MASK_7,
|
||||
UP_INT_MASK_8,
|
||||
UP_INT_MASK_9,
|
||||
UP_INT_MASK_10,
|
||||
UP_INT_MASK_11,
|
||||
UP_INT_MASK_12,
|
||||
UP_INT_MASK_13,
|
||||
UP_INT_MASK_14,
|
||||
UP_INT_MASK_15,
|
||||
UP_THRESH_0, /* UPPER threshold values */
|
||||
UP_THRESH_1,
|
||||
UP_THRESH_2,
|
||||
UP_THRESH_3,
|
||||
UP_THRESH_4,
|
||||
UP_THRESH_5,
|
||||
UP_THRESH_6,
|
||||
UP_THRESH_7,
|
||||
UP_THRESH_8,
|
||||
UP_THRESH_9,
|
||||
UP_THRESH_10,
|
||||
UP_THRESH_11,
|
||||
UP_THRESH_12,
|
||||
UP_THRESH_13,
|
||||
UP_THRESH_14,
|
||||
UP_THRESH_15,
|
||||
CRITICAL_STATUS_0, /* CRITICAL threshold violated */
|
||||
CRITICAL_STATUS_1,
|
||||
CRITICAL_STATUS_2,
|
||||
CRITICAL_STATUS_3,
|
||||
CRITICAL_STATUS_4,
|
||||
CRITICAL_STATUS_5,
|
||||
CRITICAL_STATUS_6,
|
||||
CRITICAL_STATUS_7,
|
||||
CRITICAL_STATUS_8,
|
||||
CRITICAL_STATUS_9,
|
||||
CRITICAL_STATUS_10,
|
||||
CRITICAL_STATUS_11,
|
||||
CRITICAL_STATUS_12,
|
||||
CRITICAL_STATUS_13,
|
||||
CRITICAL_STATUS_14,
|
||||
CRITICAL_STATUS_15,
|
||||
MIN_STATUS_0, /* MIN threshold violated */
|
||||
MIN_STATUS_1,
|
||||
MIN_STATUS_2,
|
||||
|
|
@ -179,61 +406,6 @@ enum regfield_ids {
|
|||
MAX_STATUS_13,
|
||||
MAX_STATUS_14,
|
||||
MAX_STATUS_15,
|
||||
LOWER_STATUS_0, /* LOWER threshold violated */
|
||||
LOWER_STATUS_1,
|
||||
LOWER_STATUS_2,
|
||||
LOWER_STATUS_3,
|
||||
LOWER_STATUS_4,
|
||||
LOWER_STATUS_5,
|
||||
LOWER_STATUS_6,
|
||||
LOWER_STATUS_7,
|
||||
LOWER_STATUS_8,
|
||||
LOWER_STATUS_9,
|
||||
LOWER_STATUS_10,
|
||||
LOWER_STATUS_11,
|
||||
LOWER_STATUS_12,
|
||||
LOWER_STATUS_13,
|
||||
LOWER_STATUS_14,
|
||||
LOWER_STATUS_15,
|
||||
UPPER_STATUS_0, /* UPPER threshold violated */
|
||||
UPPER_STATUS_1,
|
||||
UPPER_STATUS_2,
|
||||
UPPER_STATUS_3,
|
||||
UPPER_STATUS_4,
|
||||
UPPER_STATUS_5,
|
||||
UPPER_STATUS_6,
|
||||
UPPER_STATUS_7,
|
||||
UPPER_STATUS_8,
|
||||
UPPER_STATUS_9,
|
||||
UPPER_STATUS_10,
|
||||
UPPER_STATUS_11,
|
||||
UPPER_STATUS_12,
|
||||
UPPER_STATUS_13,
|
||||
UPPER_STATUS_14,
|
||||
UPPER_STATUS_15,
|
||||
CRITICAL_STATUS_0, /* CRITICAL threshold violated */
|
||||
CRITICAL_STATUS_1,
|
||||
CRITICAL_STATUS_2,
|
||||
CRITICAL_STATUS_3,
|
||||
CRITICAL_STATUS_4,
|
||||
CRITICAL_STATUS_5,
|
||||
CRITICAL_STATUS_6,
|
||||
CRITICAL_STATUS_7,
|
||||
CRITICAL_STATUS_8,
|
||||
CRITICAL_STATUS_9,
|
||||
CRITICAL_STATUS_10,
|
||||
CRITICAL_STATUS_11,
|
||||
CRITICAL_STATUS_12,
|
||||
CRITICAL_STATUS_13,
|
||||
CRITICAL_STATUS_14,
|
||||
CRITICAL_STATUS_15,
|
||||
/* TRDY */
|
||||
TRDY,
|
||||
/* INTERRUPT ENABLE */
|
||||
INT_EN, /* Pre-V1, V1.x */
|
||||
LOW_INT_EN, /* V2.x */
|
||||
UP_INT_EN, /* V2.x */
|
||||
CRIT_INT_EN, /* V2.x */
|
||||
|
||||
/* Keep last */
|
||||
MAX_REGFIELDS
|
||||
|
|
@ -303,6 +475,10 @@ struct tsens_priv {
|
|||
struct regmap *tm_map;
|
||||
struct regmap *srot_map;
|
||||
u32 tm_offset;
|
||||
|
||||
/* lock for upper/lower threshold interrupts */
|
||||
spinlock_t ul_lock;
|
||||
|
||||
struct regmap_field *rf[MAX_REGFIELDS];
|
||||
struct tsens_context ctx;
|
||||
const struct tsens_features *feat;
|
||||
|
|
@ -320,6 +496,10 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo
|
|||
int init_common(struct tsens_priv *priv);
|
||||
int get_temp_tsens_valid(struct tsens_sensor *s, int *temp);
|
||||
int get_temp_common(struct tsens_sensor *s, int *temp);
|
||||
int tsens_enable_irq(struct tsens_priv *priv);
|
||||
void tsens_disable_irq(struct tsens_priv *priv);
|
||||
int tsens_set_trips(void *_sensor, int low, int high);
|
||||
irqreturn_t tsens_irq_thread(int irq, void *data);
|
||||
|
||||
/* TSENS target */
|
||||
extern const struct tsens_plat_data data_8960;
|
||||
|
|
|
|||
Loading…
Reference in New Issue