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mmc: renesas_sdhi: add quirk for broken register layout
[ Upstream commit ec9e80ae17
]
Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20221006190452.5316-5-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
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2 changed files with 4 additions and 1 deletions
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@ -44,6 +44,7 @@ struct renesas_sdhi_quirks {
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bool fixed_addr_mode;
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bool dma_one_rx_only;
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bool manual_tap_correction;
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bool old_info1_layout;
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u32 hs400_bad_taps;
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const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
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};
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@ -49,7 +49,8 @@
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/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
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#define INFO1_CLEAR 0
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#define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
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#define INFO1_DTRANEND1 BIT(17)
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#define INFO1_DTRANEND1 BIT(20)
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#define INFO1_DTRANEND1_OLD BIT(17)
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#define INFO1_DTRANEND0 BIT(16)
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/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
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@ -165,6 +166,7 @@ static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = {
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.hs400_disabled = true,
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.hs400_4taps = true,
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.dma_one_rx_only = true,
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.old_info1_layout = true,
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};
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static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
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