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Qualcomm clock updates for 6.2

Browse source 
This introduces Global clock controller for SM8550, Display clock
 controller for SC8280XP and RPMh clock controller for QDU1000 and
 QRU1000.
 
 The SM8150/SM8250 Display clock controller is cleaned up and some
 missing clocks for SM8350 are added.
 
 MSM8974 Global and Multimedia clock controllers are transitioned to
 parent_data and parent_hws.
 
 IPQ8074 parent_data and additional network resets and the Krait clock
 controller modernized.
 
 pm_runtime usage in SC7180 and SC7280 LPASS clock controllers are
 corrected. SM8250 USB GDSCs enable retention mode.
 
 RPM and RPMh clock drivers are cleaned up, to avoid duplicating clocks
 which definition could be shared between platforms.
 
 A variety of DT binding improvements.
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Merge tag 'qcom-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

This introduces Global clock controller for SM8550, Display clock
controller for SC8280XP and RPMh clock controller for QDU1000 and
QRU1000.

The SM8150/SM8250 Display clock controller is cleaned up and some
missing clocks for SM8350 are added.

MSM8974 Global and Multimedia clock controllers are transitioned to
parent_data and parent_hws.

IPQ8074 parent_data and additional network resets and the Krait clock
controller modernized.

pm_runtime usage in SC7180 and SC7280 LPASS clock controllers are
corrected. SM8250 USB GDSCs enable retention mode.

RPM and RPMh clock drivers are cleaned up, to avoid duplicating clocks
which definition could be shared between platforms.

A variety of DT binding improvements.

* tag 'qcom-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (69 commits)
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_register
  clk: qcom: rpmh: remove usage of platform name
  clk: qcom: rpmh: rename VRM clock data
  clk: qcom: rpmh: rename ARC clock data
  clk: qcom: rpmh: support separate symbol name for the RPMH clocks
  clk: qcom: rpmh: remove platform names from BCM clocks
  clk: qcom: rpmh: drop all _ao names
  clk: qcom: rpmh: reuse common duplicate clocks
  clk: qcom: rpmh: group clock definitions together
  clk: qcom: rpm: drop the platform from clock definitions
  clk: qcom: rpm: drop the _clk suffix completely
  ...
This commit is contained in:
Stephen Boyd 2022-12-07 13:54:41 -08:00
commit 63cd992e51
102 changed files with 10608 additions and 2552 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A53 PLL Binding
title: Qualcomm A53 PLL clock
maintainers:
- Bjorn Andersson <andersson@kernel.org>

2
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A7 PLL Binding
title: Qualcomm A7 PLL clock
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

11
Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
title: LPASS Always ON Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@ -17,7 +17,7 @@ description: |
properties:
compatible:
const: qcom,sm8250-lpass-aon
const: qcom,sm8250-lpass-aoncc
reg:
maxItems: 1
@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
@ -50,9 +52,10 @@ examples:
#include <dt-bindings/sound/qcom,q6afe.h>
clock-controller@3800000 {
#clock-cells = <1>;
compatible = "qcom,sm8250-lpass-aon";
compatible = "qcom,sm8250-lpass-aoncc";
reg = <0x03380000 0x40000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};

7
Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
title: LPASS Audio Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
@ -53,6 +55,7 @@ examples:
compatible = "qcom,sm8250-lpass-audiocc";
reg = <0x03300000 0x30000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};

6
Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
View file

@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
title: Qualcomm Camera Clock & Reset Controller on SM8250
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8250.
See also dt-bindings/clock/qcom,camcc-sm8250.h
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
properties:
compatible:

97
Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml Normal file
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@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the two MDSS instances on SC8280XP.
See also:
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-dispcc0
- qcom,sc8280xp-dispcc1
clocks:
items:
- description: AHB interface clock,
- description: SoC CXO clock
- description: SoC sleep clock
- description: DisplayPort 0 link clock
- description: DisplayPort 0 VCO div clock
- description: DisplayPort 1 link clock
- description: DisplayPort 1 VCO div clock
- description: DisplayPort 2 link clock
- description: DisplayPort 2 VCO div clock
- description: DisplayPort 3 link clock
- description: DisplayPort 3 VCO div clock
- description: DSI 0 PLL byte clock
- description: DSI 0 PLL DSI clock
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
items:
- description: MMCX power domain
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sc8280xp-dispcc0";
reg = <0x0af00000 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss0_dp_phy0 0>,
<&mdss0_dp_phy0 1>,
<&mdss0_dp_phy1 0>,
<&mdss0_dp_phy1 1>,
<&mdss0_dp_phy2 0>,
<&mdss0_dp_phy2 1>,
<&mdss0_dp_phy3 0>,
<&mdss0_dp_phy3 1>,
<&mdss0_dsi0_phy 0>,
<&mdss0_dsi0_phy 1>,
<&mdss0_dsi1_phy 0>,
<&mdss0_dsi1_phy 1>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

9
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock Controller Binding for SM6125
title: Qualcomm Display Clock Controller on SM6125
maintainers:
- Martin Botka <martin.botka@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6125.
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also:
dt-bindings/clock/qcom,dispcc-sm6125.h
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:

8
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM6350
title: Qualcomm Display Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM6350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6350.
See also dt-bindings/clock/qcom,dispcc-sm6350.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
properties:
compatible:

14
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
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@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8150/SM8250/SM8350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8150/SM8250/SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
dt-bindings/clock/qcom,dispcc-sm8350.h
See also::
include/dt-bindings/clock/qcom,dispcc-sm8150.h
include/dt-bindings/clock/qcom,dispcc-sm8250.h
include/dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:

18
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
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@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8064.
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8960.h
include/dt-bindings/reset/qcom,gcc-msm8960.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:

10
Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
View file

@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
title: Qualcomm Global Clock & Reset Controller on APQ8084
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8084.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8084.
See also::
- dt-bindings/clock/qcom,gcc-apq8084.h
- dt-bindings/reset/qcom,gcc-apq8084.h
include/dt-bindings/clock/qcom,gcc-apq8084.h
include/dt-bindings/reset/qcom,gcc-apq8084.h
allOf:
- $ref: qcom,gcc.yaml#

27
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
View file

@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ8064
maintainers:
- Ansuel Smith <ansuelsmth@gmail.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8064.
See also:
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
See also::
include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
@ -27,14 +27,18 @@ properties:
- const: syscon
clocks:
minItems: 2
items:
- description: PXO source
- description: CXO source
- description: PLL4 from LCC
clock-names:
minItems: 2
items:
- const: pxo
- const: cxo
- const: pll4
thermal-sensor:
type: object
@ -51,13 +55,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064", "syscon";
reg = <0x00900000 0x4000>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
clock-names = "pxo", "cxo", "pll4";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

40
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
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@ -4,47 +4,39 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
title: Qualcomm Global Clock & Reset Controller on IPQ8074
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8074.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8074.
See also:
- dt-bindings/clock/qcom,gcc-ipq8074.h
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq8074
'#clock-cells':
const: 1
clocks:
items:
- description: board XO clock
- description: sleep clock
'#power-domain-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- reg
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |

12
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
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@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
title: Qualcomm Global Clock & Reset Controller on MSM8660
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks and resets on
Qualcomm global clock control module provides the clocks and resets on
MSM8660
See also:
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8660.h
include/dt-bindings/reset/qcom,gcc-msm8660.h
allOf:
- $ref: "qcom,gcc.yaml#"
- $ref: qcom,gcc.yaml#
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
title: Qualcomm Global Clock & Reset Controller on MSM8909
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8909.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909.
See also:
- dt-bindings/clock/qcom,gcc-msm8909.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
properties:
compatible:

16
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
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@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8916 or MSM8939.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8916 or MSM8939.
See also:
- dt-bindings/clock/qcom,gcc-msm8916.h
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/reset/qcom,gcc-msm8916.h
- dt-bindings/reset/qcom,gcc-msm8939.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8916.h
include/dt-bindings/clock/qcom,gcc-msm8939.h
include/dt-bindings/reset/qcom,gcc-msm8916.h
include/dt-bindings/reset/qcom,gcc-msm8939.h
properties:
compatible:

61
Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8974 (all variants) and MSM8226.
See also::
include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
$ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-msm8226
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@fc400000 {
compatible = "qcom,gcc-msm8974";
reg = <0x00100000 0x94000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
...

9
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
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@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
title: Qualcomm Global Clock & Reset Controller on MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8976.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8976.
See also:
- dt-bindings/clock/qcom,gcc-msm8976.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8994
title: Qualcomm Global Clock & Reset Controller on MSM8994
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8994 and MSM8992.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8994 and MSM8992.
See also:
- dt-bindings/clock/qcom,gcc-msm8994.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
properties:
compatible:

7
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
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@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
title: Qualcomm Global Clock & Reset Controller on MSM8996
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module which provides the clocks, resets and
power domains on MSM8996.
See also:
- dt-bindings/clock/qcom,gcc-msm8996.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
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@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
title: Qualcomm Global Clock & Reset Controller on MSM8998
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8998.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8998.
See also:
- dt-bindings/clock/qcom,gcc-msm8998.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
properties:
compatible:

36
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
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@ -4,30 +4,27 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding
title: Qualcomm Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains.
Qualcomm global clock control module provides the clocks, resets and power
domains.
See also:
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-mdm9607.h
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
See also::
include/dt-bindings/clock/qcom,gcc-ipq4019.h
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
include/dt-bindings/clock/qcom,gcc-mdm9615.h
include/dt-bindings/reset/qcom,gcc-mdm9615.h
allOf:
- $ref: "qcom,gcc.yaml#"
- $ref: qcom,gcc.yaml#
properties:
compatible:
@ -35,14 +32,8 @@ properties:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8953
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660
required:
- compatible
@ -50,10 +41,9 @@ required:
unevaluatedProperties: false
examples:
# Example for GCC for MSM8974:
- |
clock-controller@900000 {
compatible = "qcom,gcc-msm8974";
compatible = "qcom,gcc-mdm9607";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;

9
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for QCM2290
title: Qualcomm Global Clock & Reset Controller on QCM2290
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets
and power domains on QCM2290.
Qualcomm global clock control module provides the clocks, resets and power
domains on QCM2290.
See also:
- dt-bindings/clock/qcom,gcc-qcm2290.h
See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
View file

@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
title: Qualcomm Global Clock & Reset Controller on QCS404
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on QCS404.
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS404.
See also:
- dt-bindings/clock/qcom,gcc-qcs404.h
See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View file

@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC7180
title: Qualcomm Global Clock & Reset Controller on SC7180
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,gcc-sc7180.h
See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
title: Qualcomm Global Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC7280.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7280.
See also:
- dt-bindings/clock/qcom,gcc-sc7280.h
See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
title: Qualcomm Global Clock & Reset Controller on SC8180x
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC8180x.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC8180x.
See also:
- dt-bindings/clock/qcom,gcc-sc8180x.h
See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
properties:
compatible:

7
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
title: Qualcomm Global Clock & Reset Controller on SC8280xp
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module provides the clocks, resets and
power domains on SC8280xp.
See also:
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
properties:
compatible:

61
Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml Normal file
View file

@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660/SDM630/SDM636 Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM630, SDM636 and SDM660
See also::
include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
$ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-sdm630
- qcom,gcc-sdm660
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
power-domains:
maxItems: 1
required:
- compatible
unevaluatedProperties: false
examples:
# Example for GCC for SDM660:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdm660";
reg = <0x00100000 0x94000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
...

9
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
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@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding
title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDM845
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM670 and SDM845
See also:
- dt-bindings/clock/qcom,gcc-sdm845.h
See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:

7
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
View file

@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX55
title: Qualcomm Global Clock & Reset Controller on SDX55
maintainers:
- Vinod Koul <vkoul@kernel.org>
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module provides the clocks, resets and
power domains on SDX55
See also:
- dt-bindings/clock/qcom,gcc-sdx55.h
See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
title: Qualcomm Global Clock & Reset Controller on SDX65
maintainers:
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDX65
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX65
See also:
- dt-bindings/clock/qcom,gcc-sdx65.h
See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6115 and SM4250
title: Qualcomm Global Clock & Reset Controller on SM6115 and SM4250
maintainers:
- Iskren Chernev <iskren.chernev@gmail.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM4250/6115.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM4250/6115.
See also:
- dt-bindings/clock/qcom,gcc-sm6115.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
title: Qualcomm Global Clock & Reset Controller on SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6125.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6125.
See also:
- dt-bindings/clock/qcom,gcc-sm6125.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6350
title: Qualcomm Global Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6350.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6350.
See also:
- dt-bindings/clock/qcom,gcc-sm6350.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View file

@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8150
title: Qualcomm Global Clock & Reset Controller on SM8150
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8150.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8150.
See also:
- dt-bindings/clock/qcom,gcc-sm8150.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View file

@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8250
title: Qualcomm Global Clock & Reset Controller on SM8250
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8250.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8250.
See also:
- dt-bindings/clock/qcom,gcc-sm8250.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
title: Qualcomm Global Clock & Reset Controller on SM8350
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8350.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8350.
See also:
- dt-bindings/clock/qcom,gcc-sm8350.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
properties:
compatible:

9
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8450
title: Qualcomm Global Clock & Reset Controller on SM8450
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8450
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8450
See also:
- dt-bindings/clock/qcom,gcc-sm8450.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
properties:
compatible:

6
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View file

@ -4,15 +4,15 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
title: Qualcomm Global Clock & Reset Controller Common Bindings
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Common bindings for Qualcomm global clock control module which supports
the clocks, resets and power domains.
Common bindings for Qualcomm global clock control module providing the
clocks, resets and power domains.
properties:
'#clock-cells':

4
Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml
View file

@ -4,13 +4,13 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
Qualcomm graphics clock control module provides the clocks, resets and
power domains on SDM630 and SDM660.
See also dt-bindings/clock/qcom,gpucc-sdm660.h.

9
Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
View file

@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding
title: Qualcomm Graphics Clock & Reset Controller on SM8350
maintainers:
- Robert Foss <robert.foss@linaro.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,gpucc-sm8350.h
See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h
properties:
compatible:

22
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
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@ -4,23 +4,23 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding
title: Qualcomm Graphics Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
dt-bindings/clock/qcom,gpucc-sc8280xp.h
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
See also::
include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
include/dt-bindings/clock/qcom,gpucc-sm6350.h
include/dt-bindings/clock/qcom,gpucc-sm8150.h
include/dt-bindings/clock/qcom,gpucc-sm8250.h
properties:
compatible:

22
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@ -1,22 +0,0 @@
Qualcomm LPASS Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,lcc-msm8960"
"qcom,lcc-apq8064"
"qcom,lcc-ipq8064"
"qcom,lcc-mdm9615"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
Example:
clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

86
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Clock & Reset Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
- qcom,lcc-apq8064
- qcom,lcc-ipq8064
- qcom,lcc-mdm9615
- qcom,lcc-msm8960
clocks:
maxItems: 8
clock-names:
maxItems: 8
'#clock-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,lcc-apq8064
- qcom,lcc-msm8960
then:
properties:
clocks:
items:
- description: Board PXO source
- description: PLL 4 Vote clock
- description: MI2S codec clock
- description: Mic I2S codec clock
- description: Mic I2S spare clock
- description: Speaker I2S codec clock
- description: Speaker I2S spare clock
- description: PCM codec clock
clock-names:
items:
- const: pxo
- const: pll4_vote
- const: mi2s_codec_clk
- const: codec_i2s_mic_codec_clk
- const: spare_i2s_mic_codec_clk
- const: codec_i2s_spkr_codec_clk
- const: spare_i2s_spkr_codec_clk
- const: pcm_codec_clk
required:
- clocks
- clock-names
examples:
- |
clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

26
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@ -1,26 +0,0 @@
Qualcomm LPASS Clock Controller Binding
-----------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-lpasscc"
- #clock-cells : from common clock binding, shall contain 1.
- reg : shall contain base register address and size,
in the order
Index-0 maps to LPASS_CC register region
Index-1 maps to LPASS_QDSP6SS register region
Optional properties :
- reg-names : register names of LPASS domain
"cc", "qdsp6ss".
Example:
The below node has to be defined in the cases where the LPASS peripheral loader
would bring the subsystem out of reset.
lpasscc: clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
reg-names = "cc", "qdsp6ss";
#clock-cells = <1>;
};

42
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@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Multimedia Clock & Reset Controller Binding
title: Qualcomm Multimedia Clock & Reset Controller
maintainers:
- Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm multimedia clock control module which supports the clocks, resets and
Qualcomm multimedia clock control module provides the clocks, resets and
power domains.
properties:
@ -99,6 +99,44 @@ allOf:
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8974
then:
properties:
clocks:
items:
- description: Board XO source
- description: MMSS GPLL0 voted clock
- description: GPLL0 voted clock
- description: GPLL1 voted clock
- description: GFX3D clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
- description: eDP phy PLL link clock
- description: eDP phy PLL vco clock
clock-names:
items:
- const: xo
- const: mmss_gpll0_vote
- const: gpll0_vote
- const: gpll1_vote
- const: gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- const: edp_link_clk
- const: edp_vco_div
- if:
properties:
compatible:

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
title: Qualcomm Graphics Clock & Reset Controller on MSM8998
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on MSM8998.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on MSM8998.
See also dt-bindings/clock/qcom,gpucc-msm8998.h.
See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h
properties:
compatible:

2
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@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
const: "qcom,qcs404-q6sstopcc"
const: qcom,qcs404-q6sstopcc
reg:
items:

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
title: Qualcomm Display Clock & Reset Controller on QCM2290
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on qcm2290.
Qualcomm display clock control module provides the clocks, resets and power
domains on qcm2290.
See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
properties:
compatible:

1
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@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,qdu1000-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk

9
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7180
title: Qualcomm Camera Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,camcc-sc7180.h
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
properties:
compatible:

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC7180
title: Qualcomm Display Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7180.
See also dt-bindings/clock/qcom,dispcc-sc7180.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:

9
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller Binding for SC7180
title: Qualcomm LPASS Core Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core clock control module which supports the clocks and
power domains on SC7180.
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
properties:
compatible:

7
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@ -4,16 +4,15 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Modem Clock Controller Binding for SC7180
title: Qualcomm Modem Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm modem clock control module which supports the clocks on SC7180.
Qualcomm modem clock control module provides the clocks on SC7180.
See also:
- dt-bindings/clock/qcom,mss-sc7180.h
See also:: include/dt-bindings/clock/qcom,mss-sc7180.h
properties:
compatible:

6
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
title: Qualcomm Camera Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
Qualcomm camera clock control module provides the clocks, resets and
power domains on SC7280.
See also dt-bindings/clock/qcom,camcc-sc7280.h
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
properties:
compatible:

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC7280
title: Qualcomm Display Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SC7280.
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7280.
See also dt-bindings/clock/qcom,dispcc-sc7280.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
properties:
compatible:

9
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller Binding for SC7280
title: Qualcomm LPASS Core Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core clock control module which supports the clocks and
power domains on SC7280.
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpass-sc7280.h
See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
properties:
compatible:

12
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@ -4,18 +4,18 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core and audio clock control module which supports the
clocks and power domains on SC7280.
Qualcomm LPASS core and audio clock control module provides the clocks and
power domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
See also::
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
clocks: true

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
title: Qualcomm Camera Clock & Reset Controller on SDM845
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SDM845.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SDM845.
See also dt-bindings/clock/qcom,camcc-sm845.h
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
properties:
compatible:

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SDM845
title: Qualcomm Display Clock & Reset Controller on SDM845
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SDM845.
Qualcomm display clock control module provides the clocks, resets and power
domains on SDM845.
See also dt-bindings/clock/qcom,dispcc-sdm845.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h
properties:
compatible:

47
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@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM845 LPASS Clock Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller.
See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h
properties:
compatible:
const: qcom,sdm845-lpasscc
'#clock-cells':
const: 1
reg:
maxItems: 2
reg-names:
items:
- const: cc
- const: qdsp6ss
required:
- compatible
- '#clock-cells'
- reg
- reg-names
additionalProperties: false
examples:
- |
clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
reg-names = "cc", "qdsp6ss";
#clock-cells = <1>;
};

7
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
View file

@ -10,11 +10,10 @@ maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6115.
Qualcomm display clock control module provides the clocks and power domains
on SM6115.
See also:
include/dt-bindings/clock/qcom,sm6115-dispcc.h
See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
properties:
compatible:

54
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6375.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm6375-dispcc
clocks:
items:
- description: Board XO source
- description: GPLL0 source from GCC
- description: Byte clock from DSI PHY
- description: Pixel clock from DSI PHY
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@5f00000 {
compatible = "qcom,sm6375-dispcc";
reg = <0x05f00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

9
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@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6375
title: Qualcomm Global Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6375
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6375
See also:
- dt-bindings/clock/qcom,sm6375-gcc.h
See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h
allOf:
- $ref: qcom,gcc.yaml#

8
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@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SM8450.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also include/dt-bindings/clock/qcom,sm8450-camcc.h
See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
properties:
compatible:

7
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
View file

@ -10,11 +10,10 @@ maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8450.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,sm8450-dispcc.h
See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
properties:
compatible:

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@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
properties:
compatible:
const: qcom,sm8550-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: PCIE 1 Phy Auxiliary clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8550-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie_1_phy_aux_clk>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

18
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@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller Binding
title: Qualcomm Video Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,videocc-sc7180.h
dt-bindings/clock/qcom,videocc-sc7280.h
dt-bindings/clock/qcom,videocc-sdm845.h
dt-bindings/clock/qcom,videocc-sm8150.h
dt-bindings/clock/qcom,videocc-sm8250.h
See also::
include/dt-bindings/clock/qcom,videocc-sc7180.h
include/dt-bindings/clock/qcom,videocc-sc7280.h
include/dt-bindings/clock/qcom,videocc-sdm845.h
include/dt-bindings/clock/qcom,videocc-sm8150.h
include/dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:

26
drivers/clk/qcom/Kconfig
View file

@ -401,6 +401,15 @@ config SC_DISPCC_7280
Say Y if you want to support display devices and functionality such as
splash screen.
config SC_DISPCC_8280XP
tristate "SC8280XP Display Clock Controller"
select SC_GCC_8280XP
help
Support for the two display clock controllers on Qualcomm
Technologies, Inc. SC8280XP devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SC_GCC_7180
tristate "SC7180 Global Clock Controller"
select QCOM_GDSC
@ -668,6 +677,15 @@ config SM_DISPCC_6350
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_6375
tristate "SM6375 Display Clock Controller"
depends on SM_GCC_6375
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM6375 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_8450
tristate "SM8450 Display Clock Controller"
depends on SM_GCC_8450
@ -739,6 +757,14 @@ config SM_GCC_8450
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8550
tristate "SM8550 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM8550 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_6350
tristate "SM6350 Graphics Clock Controller"
select SM_GCC_6350

3
drivers/clk/qcom/Makefile
View file

@ -66,6 +66,7 @@ obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
@ -95,6 +96,7 @@ obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
@ -105,6 +107,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o

16
drivers/clk/qcom/clk-alpha-pll.c
View file

@ -155,6 +155,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATE] = 0x08,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U2] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,

5
drivers/clk/qcom/clk-alpha-pll.h
View file

@ -18,6 +18,7 @@ enum {
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
@ -38,6 +39,8 @@ enum {
PLL_OFF_TEST_CTL,
PLL_OFF_TEST_CTL_U,
PLL_OFF_TEST_CTL_U1,
PLL_OFF_TEST_CTL_U2,
PLL_OFF_STATE,
PLL_OFF_STATUS,
PLL_OFF_OPMODE,
PLL_OFF_FRAC,
@ -160,7 +163,9 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops

2
drivers/clk/qcom/clk-krait.c
View file

@ -114,6 +114,8 @@ static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
if (d->lpl)
mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
else
mask <<= d->shift;
spin_lock_irqsave(&krait_clock_reg_lock, flags);
val = krait_get_l2_indirect_reg(d->offset);

204
drivers/clk/qcom/clk-rpm.c
View file

@ -31,51 +31,51 @@ static const struct clk_parent_data gcc_cxo[] = {
{ .fw_name = "cxo", .name = "cxo_board" },
};
#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
static struct clk_rpm _platform##_##_active; \
static struct clk_rpm _platform##_##_name = { \
#define DEFINE_CLK_RPM(_name, r_id) \
static struct clk_rpm clk_rpm_##_name##_a_clk; \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = (r_id), \
.peer = &_platform##_##_active, \
.peer = &clk_rpm_##_name##_a_clk, \
.rate = INT_MAX, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_ops, \
.name = #_name, \
.name = #_name "_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
}; \
static struct clk_rpm _platform##_##_active = { \
static struct clk_rpm clk_rpm_##_name##_a_clk = { \
.rpm_clk_id = (r_id), \
.peer = &_platform##_##_name, \
.peer = &clk_rpm_##_name##_clk, \
.active_only = true, \
.rate = INT_MAX, \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_ops, \
.name = #_active, \
.name = #_name "_a_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
}
#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \
static struct clk_rpm _platform##_##_name = { \
#define DEFINE_CLK_RPM_XO_BUFFER(_name, offset) \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
.xo_offset = (offset), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_xo_ops, \
.name = #_name, \
.ops = &clk_rpm_xo_ops, \
.name = #_name "_clk", \
.parent_data = gcc_cxo, \
.num_parents = ARRAY_SIZE(gcc_cxo), \
}, \
}
#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \
static struct clk_rpm _platform##_##_name = { \
#define DEFINE_CLK_RPM_FIXED(_name, r_id, r) \
static struct clk_rpm clk_rpm_##_name##_clk = { \
.rpm_clk_id = (r_id), \
.rate = (r), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpm_fixed_ops, \
.name = #_name, \
.name = #_name "_clk", \
.parent_data = gcc_pxo, \
.num_parents = ARRAY_SIZE(gcc_pxo), \
}, \
@ -402,38 +402,48 @@ static const struct clk_ops clk_rpm_ops = {
.recalc_rate = clk_rpm_recalc_rate,
};
/* MSM8660/APQ8060 */
DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
static struct clk_rpm *msm8660_clks[] = {
[RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
[RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
[RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
[RPM_SFPB_CLK] = &msm8660_sfpb_clk,
[RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
[RPM_CFPB_CLK] = &msm8660_cfpb_clk,
[RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
[RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
[RPM_SMI_CLK] = &msm8660_smi_clk,
[RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
[RPM_EBI1_CLK] = &msm8660_ebi1_clk,
[RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
[RPM_PLL4_CLK] = &msm8660_pll4_clk,
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
[RPM_SMI_CLK] = &clk_rpm_smi_clk,
[RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
};
static const struct rpm_clk_desc rpm_clk_msm8660 = {
@ -441,46 +451,30 @@ static const struct rpm_clk_desc rpm_clk_msm8660 = {
.num_clks = ARRAY_SIZE(msm8660_clks),
};
/* apq8064 */
DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0);
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8);
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16);
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
static struct clk_rpm *apq8064_clks[] = {
[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
[RPM_CFPB_CLK] = &apq8064_cfpb_clk,
[RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
[RPM_EBI1_CLK] = &apq8064_ebi1_clk,
[RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
[RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
[RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
[RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
[RPM_SFPB_CLK] = &apq8064_sfpb_clk,
[RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
[RPM_QDSS_CLK] = &apq8064_qdss_clk,
[RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
[RPM_XO_D0] = &apq8064_xo_d0_clk,
[RPM_XO_D1] = &apq8064_xo_d1_clk,
[RPM_XO_A0] = &apq8064_xo_a0_clk,
[RPM_XO_A1] = &apq8064_xo_a1_clk,
[RPM_XO_A2] = &apq8064_xo_a2_clk,
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
[RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
[RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
[RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
[RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
[RPM_XO_D0] = &clk_rpm_xo_d0_clk,
[RPM_XO_D1] = &clk_rpm_xo_d1_clk,
[RPM_XO_A0] = &clk_rpm_xo_a0_clk,
[RPM_XO_A1] = &clk_rpm_xo_a1_clk,
[RPM_XO_A2] = &clk_rpm_xo_a2_clk,
};
static const struct rpm_clk_desc rpm_clk_apq8064 = {
@ -488,33 +482,23 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = {
.num_clks = ARRAY_SIZE(apq8064_clks),
};
/* ipq806x */
DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
static struct clk_rpm *ipq806x_clks[] = {
[RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
[RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
[RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
[RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
[RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
[RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
[RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
[RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
[RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
[RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
[RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
[RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
[RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
[RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
[RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
[RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
[RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
[RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
[RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
[RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
[RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
[RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
[RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
[RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
[RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
[RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
[RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
[RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
};
static const struct rpm_clk_desc rpm_clk_ipq806x = {

427
drivers/clk/qcom/clk-rpmh.c
View file

@ -70,15 +70,15 @@ struct clk_rpmh_desc {
static DEFINE_MUTEX(rpmh_clk_lock);
#define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
#define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \
_res_en_offset, _res_on, _div) \
static struct clk_rpmh _platform##_##_name_active; \
static struct clk_rpmh _platform##_##_name = { \
static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \
static struct clk_rpmh clk_rpmh_##_clk_name = { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
.peer = &_platform##_##_name_active, \
.peer = &clk_rpmh_##_clk_name##_ao, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE) | \
BIT(RPMH_SLEEP_STATE)), \
@ -92,17 +92,17 @@ static DEFINE_MUTEX(rpmh_clk_lock);
.num_parents = 1, \
}, \
}; \
static struct clk_rpmh _platform##_##_name_active = { \
static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \
.res_name = _res_name, \
.res_addr = _res_en_offset, \
.res_on_val = _res_on, \
.div = _div, \
.peer = &_platform##_##_name, \
.peer = &clk_rpmh_##_clk_name, \
.valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
BIT(RPMH_ACTIVE_ONLY_STATE)), \
.hw.init = &(struct clk_init_data){ \
.ops = &clk_rpmh_ops, \
.name = #_name_active, \
.name = #_name "_ao", \
.parent_data = &(const struct clk_parent_data){ \
.fw_name = "xo", \
.name = "xo_board", \
@ -111,18 +111,16 @@ static DEFINE_MUTEX(rpmh_clk_lock);
}, \
}
#define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
_res_on, _div) \
__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
#define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \
__DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \
CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
#define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
_div) \
__DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
#define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \
__DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \
CLK_RPMH_VRM_EN_OFFSET, 1, _div)
#define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
static struct clk_rpmh _platform##_##_name = { \
#define DEFINE_CLK_RPMH_BCM(_name, _res_name) \
static struct clk_rpmh clk_rpmh_##_name = { \
.res_name = _res_name, \
.valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
.div = 1, \
@ -342,35 +340,55 @@ static const struct clk_ops clk_rpmh_bcm_ops = {
};
/* Resource name must match resource id present in cmd-db */
DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk3, rf_clk3_ao, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(sc8180x, rf_clk4, rf_clk4_ao, "rfclkd4", 1);
DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
DEFINE_CLK_RPMH_BCM(sdm845, ce, "CE0");
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2);
DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1);
DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1);
DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1);
DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1);
DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1);
DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1);
DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1);
DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1);
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
DEFINE_CLK_RPMH_BCM(ipa, "IP0");
DEFINE_CLK_RPMH_BCM(pka, "PKA0");
DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0");
static struct clk_hw *sdm845_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_CE_CLK] = &sdm845_ce.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
@ -379,18 +397,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
};
static struct clk_hw *sdm670_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_CE_CLK] = &sdm845_ce.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_CE_CLK] = &clk_rpmh_ce.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
@ -398,20 +416,15 @@ static const struct clk_rpmh_desc clk_rpmh_sdm670 = {
.num_clks = ARRAY_SIZE(sdm670_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
DEFINE_CLK_RPMH_BCM(sdx55, ipa, "IP0");
static struct clk_hw *sdx55_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_RF_CLK1] = &sdx55_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdx55_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw,
[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
[RPMH_IPA_CLK] = &sdx55_ipa.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
@ -420,18 +433,18 @@ static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
};
static struct clk_hw *sm8150_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
@ -440,17 +453,17 @@ static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
};
static struct clk_hw *sc7180_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
@ -459,18 +472,18 @@ static const struct clk_rpmh_desc clk_rpmh_sc7180 = {
};
static struct clk_hw *sc8180x_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sc8180x_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sc8180x_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sc8180x_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sc8180x_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sc8180x_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sc8180x_rf_clk3_ao.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
@ -478,21 +491,19 @@ static const struct clk_rpmh_desc clk_rpmh_sc8180x = {
.num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
static struct clk_hw *sm8250_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
@ -500,32 +511,26 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");
static struct clk_hw *sm8350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
[RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_RF_CLK5] = &sm8350_rf_clk5.hw,
[RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_PKA_CLK] = &sm8350_pka.hw,
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw,
[RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
@ -533,16 +538,14 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sc8280xp, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
static struct clk_hw *sc8280xp_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK3] = &sc8280xp_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sc8280xp_ln_bb_clk3_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_PKA_CLK] = &sm8350_pka.hw,
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
@ -550,28 +553,22 @@ static const struct clk_rpmh_desc clk_rpmh_sc8280xp = {
.num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks),
};
/* Resource name must match resource id present in cmd-db */
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
DEFINE_CLK_RPMH_VRM(sm8450, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 4);
static struct clk_hw *sm8450_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK1] = &sm8450_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sm8450_ln_bb_clk1_ao.hw,
[RPMH_LN_BB_CLK2] = &sm8450_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sm8450_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
@ -580,19 +577,19 @@ static const struct clk_rpmh_desc clk_rpmh_sm8450 = {
};
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_PKA_CLK] = &sm8350_pka.hw,
[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_PKA_CLK] = &clk_rpmh_pka.hw,
[RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
@ -600,19 +597,16 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
static struct clk_hw *sm6350_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
[RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
[RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
[RPMH_QLINK_CLK] = &sm6350_qlink.hw,
[RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw,
[RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw,
[RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
@ -620,23 +614,21 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
};
DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
static struct clk_hw *sdx65_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK1] = &sdx65_ln_bb_clk1.hw,
[RPMH_LN_BB_CLK1_A] = &sdx65_ln_bb_clk1_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
[RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
[RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
[RPMH_IPA_CLK] = &sdm845_ipa.hw,
[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
[RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw,
};
static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
@ -644,6 +636,16 @@ static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
};
static struct clk_hw *qdu1000_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_qdu1000 = {
.clks = qdu1000_rpmh_clocks,
.num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@ -727,6 +729,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
}
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
{ .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},

3218
drivers/clk/qcom/dispcc-sc8280xp.c Normal file
View file

File diff suppressed because it is too large Load diff

4
drivers/clk/qcom/dispcc-sm6350.c
View file

@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_5,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
@ -385,7 +385,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = {
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
.ops = &clk_branch2_ops,
},
},

610
drivers/clk/qcom/dispcc-sm6375.c Normal file
View file

@ -0,0 +1,610 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-dispcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_DISP_GPLL0_CLK,
DT_DSI0_PHY_PLL_OUT_BYTECLK,
DT_DSI0_PHY_PLL_OUT_DSICLK,
};
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_EVEN,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GCC_DISP_GPLL0_CLK,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 615MHz */
static const struct alpha_pll_config disp_cc_pll0_config = {
.l = 0x20,
.alpha = 0x800,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll disp_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map disp_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
};
static const struct parent_map disp_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
{ P_DISP_CC_PLL0_OUT_EVEN, 5 },
};
static const struct clk_parent_data disp_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &disp_cc_pll0.clkr.hw },
{ .index = DT_GCC_DISP_GPLL0_CLK },
{ .hw = &disp_cc_pll0.clkr.hw },
};
static const struct parent_map disp_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_DISP_GPLL0_CLK, 4 },
};
static const struct clk_parent_data disp_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_DISP_GPLL0_CLK },
};
static const struct parent_map disp_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
static const struct clk_parent_data disp_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
};
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(37500000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
F(75000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
.cmd_rcgr = 0x115c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_2,
.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk_src",
.parent_data = disp_cc_parent_data_2,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
.cmd_rcgr = 0x10c4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_byte2_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
.cmd_rcgr = 0x10e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_0,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk_src",
.parent_data = disp_cc_parent_data_0,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
F(373500000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(470000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
.cmd_rcgr = 0x107c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.cmd_rcgr = 0x1064,
.mnd_width = 8,
.hid_width = 5,
.parent_map = disp_cc_parent_map_3,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_3,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
F(200000000, P_GCC_DISP_GPLL0_CLK, 1.5, 0, 0),
F(300000000, P_GCC_DISP_GPLL0_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
.cmd_rcgr = 0x1094,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_1,
.freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk_src",
.parent_data = disp_cc_parent_data_1,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
.cmd_rcgr = 0x10ac,
.mnd_width = 0,
.hid_width = 5,
.parent_map = disp_cc_parent_map_4,
.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
.reg = 0x10dc,
.shift = 0,
.width = 4,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_byte0_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ops,
},
};
static struct clk_branch disp_cc_mdss_ahb_clk = {
.halt_reg = 0x104c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x104c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_clk = {
.halt_reg = 0x102c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x102c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
.halt_reg = 0x1030,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1030,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_byte0_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_byte0_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_esc0_clk = {
.halt_reg = 0x1034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1034,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_esc0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_clk = {
.halt_reg = 0x1010,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1010,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
.halt_reg = 0x1020,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1020,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_mdp_lut_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
.halt_reg = 0x2004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x2004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_non_gdsc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_pclk0_clk = {
.halt_reg = 0x1168,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1168,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_pclk0_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rot_clk = {
.halt_reg = 0x1018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rot_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_rot_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
.halt_reg = 0x200c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x200c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
.halt_reg = 0x2008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_rscc_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_mdss_vsync_clk = {
.halt_reg = 0x1028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1028,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_vsync_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_sleep_clk = {
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_sleep_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch disp_cc_xo_clk = {
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x5008,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "disp_cc_xo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x1004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
};
static struct clk_regmap *disp_cc_sm6375_clocks[] = {
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
};
static const struct qcom_reset_map disp_cc_sm6375_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
};
static struct gdsc *disp_cc_sm6375_gdscs[] = {
[MDSS_GDSC] = &mdss_gdsc,
};
static const struct regmap_config disp_cc_sm6375_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x10000,
.fast_io = true,
};
static const struct qcom_cc_desc disp_cc_sm6375_desc = {
.config = &disp_cc_sm6375_regmap_config,
.clks = disp_cc_sm6375_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6375_clocks),
.resets = disp_cc_sm6375_resets,
.num_resets = ARRAY_SIZE(disp_cc_sm6375_resets),
.gdscs = disp_cc_sm6375_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6375_gdscs),
};
static const struct of_device_id disp_cc_sm6375_match_table[] = {
{ .compatible = "qcom,sm6375-dispcc" },
{ }
};
MODULE_DEVICE_TABLE(of, disp_cc_sm6375_match_table);
static int disp_cc_sm6375_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &disp_cc_sm6375_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
}
static struct platform_driver disp_cc_sm6375_driver = {
.probe = disp_cc_sm6375_probe,
.driver = {
.name = "disp_cc-sm6375",
.of_match_table = disp_cc_sm6375_match_table,
},
};
static int __init disp_cc_sm6375_init(void)
{
return platform_driver_register(&disp_cc_sm6375_driver);
}
subsys_initcall(disp_cc_sm6375_init);
static void __exit disp_cc_sm6375_exit(void)
{
platform_driver_unregister(&disp_cc_sm6375_driver);
}
module_exit(disp_cc_sm6375_exit);
MODULE_DESCRIPTION("QTI DISPCC SM6375 Driver");
MODULE_LICENSE("GPL");

38
drivers/clk/qcom/dispcc-sm8250.c
View file

@ -462,6 +462,20 @@ static struct clk_branch disp_cc_mdss_edp_link_clk = {
},
};
static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
.reg = 0x2288,
.shift = 0,
.width = 2,
.clkr.hw.init = &(struct clk_init_data) {
.name = "disp_cc_mdss_edp_link_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.halt_reg = 0x2074,
.halt_check = BRANCH_HALT,
@ -471,7 +485,7 @@ static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
.hw.init = &(struct clk_init_data){
.name = "disp_cc_mdss_edp_link_intf_clk",
.parent_hws = (const struct clk_hw*[]){
&disp_cc_mdss_edp_link_clk_src.clkr.hw,
&disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,
@ -1137,7 +1151,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8250_clocks[] = {
@ -1175,6 +1189,7 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = {
[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
[DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
[DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
[DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
@ -1274,6 +1289,17 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_dp_link_clk_src.clkr.hw;
disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_dp_link1_clk_src.clkr.hw;
disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
&disp_cc_mdss_edp_link_clk_src.clkr.hw;
disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
static struct clk_rcg2 * const rcgs[] = {
&disp_cc_mdss_byte0_clk_src,
@ -1285,7 +1311,11 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
&disp_cc_mdss_dp_pixel1_clk_src,
&disp_cc_mdss_dp_pixel2_clk_src,
&disp_cc_mdss_dp_pixel_clk_src,
&disp_cc_mdss_edp_aux_clk_src,
&disp_cc_mdss_edp_link_clk_src,
&disp_cc_mdss_edp_pixel_clk_src,
&disp_cc_mdss_esc0_clk_src,
&disp_cc_mdss_esc1_clk_src,
&disp_cc_mdss_mdp_clk_src,
&disp_cc_mdss_pclk0_clk_src,
&disp_cc_mdss_pclk1_clk_src,
@ -1297,6 +1327,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
&disp_cc_mdss_byte1_div_clk_src,
&disp_cc_mdss_dp_link1_div_clk_src,
&disp_cc_mdss_dp_link_div_clk_src,
&disp_cc_mdss_edp_link_div_clk_src,
};
unsigned int i;
static bool offset_applied;
@ -1330,6 +1361,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
disp_cc_pll1.vco_table = lucid_5lpe_vco;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
}
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);

11
drivers/clk/qcom/gcc-ipq4019.c
View file

@ -1756,19 +1756,12 @@ static int gcc_ipq4019_probe(struct platform_device *pdev)
if (err)
return err;
return clk_notifier_register(apps_clk_src.clkr.hw.clk,
&gcc_ipq4019_cpu_clk_notifier);
}
static int gcc_ipq4019_remove(struct platform_device *pdev)
{
return clk_notifier_unregister(apps_clk_src.clkr.hw.clk,
&gcc_ipq4019_cpu_clk_notifier);
return devm_clk_notifier_register(&pdev->dev, apps_clk_src.clkr.hw.clk,
&gcc_ipq4019_cpu_clk_notifier);
}
static struct platform_driver gcc_ipq4019_driver = {
.probe = gcc_ipq4019_probe,
.remove = gcc_ipq4019_remove,
.driver = {
.name = "qcom,gcc-ipq4019",
.of_match_table = gcc_ipq4019_match_table,

4
drivers/clk/qcom/gcc-ipq806x.c
View file

@ -79,7 +79,9 @@ static struct clk_regmap pll4_vote = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "pll4_vote",
.parent_names = (const char *[]){ "pll4" },
.parent_data = &(const struct clk_parent_data){
.fw_name = "pll4", .name = "pll4",
},
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},

1795
drivers/clk/qcom/gcc-ipq8074.c
View file

File diff suppressed because it is too large Load diff

35
drivers/clk/qcom/gcc-msm8939.c
View file

@ -1033,7 +1033,20 @@ static struct clk_rcg2 cci_clk_src = {
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* See comment at ftbl_gcc_gp1_3_clk.
*/
static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(100000000, P_GPLL0, 8, 0, 0),
F(200000000, P_GPLL0, 4, 0, 0),
{ }
@ -1198,7 +1211,29 @@ static struct clk_rcg2 crypto_clk_src = {
},
};
/*
* This is a frequency table for "General Purpose" clocks.
* These clocks can be muxed to the SoC pins and may be used by
* external devices. They're often used as PWM source.
*
* Please note that MND divider must be enabled for duty-cycle
* control to be possible. (M != N) Also since D register is configured
* with a value multiplied by 2, and duty cycle is calculated as
* (2 * D) % 2^W
* DutyCycle = ----------------
* 2 * (N % 2^W)
* (where W = .mnd_width)
* N must be half or less than maximum value for the register.
* Otherwise duty-cycle control would be limited.
* (e.g. for 8-bit NMD N should be less than 128)
*/
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
F(10000, P_XO, 16, 1, 120),
F(100000, P_XO, 16, 1, 12),
F(500000, P_GPLL0, 16, 1, 100),
F(1000000, P_GPLL0, 16, 1, 50),
F(2500000, P_GPLL0, 16, 1, 20),
F(5000000, P_GPLL0, 16, 1, 10),
F(19200000, P_XO, 1, 0, 0),
{ }
};

742
drivers/clk/qcom/gcc-msm8974.c
View file

File diff suppressed because it is too large Load diff

1
drivers/clk/qcom/gcc-sm6125.c
View file

@ -1153,7 +1153,6 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
F(202000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};

4
drivers/clk/qcom/gcc-sm8250.c
View file

@ -3267,7 +3267,7 @@ static struct gdsc usb30_prim_gdsc = {
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc usb30_sec_gdsc = {
@ -3275,7 +3275,7 @@ static struct gdsc usb30_sec_gdsc = {
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {

3387
drivers/clk/qcom/gcc-sm8550.c Normal file
View file

File diff suppressed because it is too large Load diff

3
drivers/clk/qcom/gdsc.c
View file

@ -47,6 +47,7 @@
#define RETAIN_MEM BIT(14)
#define RETAIN_PERIPH BIT(13)
#define STATUS_POLL_TIMEOUT_US 1500
#define TIMEOUT_US 500
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
@ -124,7 +125,7 @@ static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
do {
if (gdsc_check_status(sc, status))
return 0;
} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
} while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);
if (gdsc_check_status(sc, status))
return 0;

4
drivers/clk/qcom/hfpll.c
View file

@ -47,7 +47,6 @@ static const struct regmap_config hfpll_regmap_config = {
static int qcom_hfpll_probe(struct platform_device *pdev)
{
struct resource *res;
struct device *dev = &pdev->dev;
void __iomem *base;
struct regmap *regmap;
@ -70,8 +69,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev)
if (!h)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
if (IS_ERR(base))
return PTR_ERR(base);

13
drivers/clk/qcom/kpss-xcc.c
View file

@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
static int kpss_xcc_driver_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
const struct of_device_id *id;
void __iomem *base;
struct clk_hw *hw;
const char *name;
id = of_match_device(kpss_xcc_match_table, &pdev->dev);
id = of_match_device(kpss_xcc_match_table, dev);
if (!id)
return -ENODEV;
@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev)
return PTR_ERR(base);
if (id->data) {
if (of_property_read_string_index(pdev->dev.of_node,
if (of_property_read_string_index(dev->of_node,
"clock-output-names",
0, &name))
return -ENODEV;
@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct platform_device *pdev)
base += 0x28;
}
hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
ARRAY_SIZE(aux_parents), 0,
base, 0, 0x3,
0, aux_parent_map, NULL);
if (IS_ERR(hw))
return PTR_ERR(hw);
return PTR_ERR_OR_ZERO(hw);
of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
return 0;
}
static struct platform_driver kpss_xcc_driver = {

238
drivers/clk/qcom/krait-cc.c
View file

@ -15,6 +15,16 @@
#include "clk-krait.h"
enum {
cpu0_mux = 0,
cpu1_mux,
cpu2_mux,
cpu3_mux,
l2_mux,
clks_max,
};
static unsigned int sec_mux_map[] = {
2,
0,
@ -62,28 +72,30 @@ static int krait_notifier_register(struct device *dev, struct clk *clk,
int ret = 0;
mux->clk_nb.notifier_call = krait_notifier_cb;
ret = clk_notifier_register(clk, &mux->clk_nb);
ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
if (ret)
dev_err(dev, "failed to register clock notifier: %d\n", ret);
return ret;
}
static int
static struct clk_hw *
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
struct krait_div2_clk *div;
static struct clk_parent_data p_data[1];
struct clk_init_data init = {
.num_parents = 1,
.num_parents = ARRAY_SIZE(p_data),
.ops = &krait_div2_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
const char *p_names[1];
struct clk *clk;
struct clk_hw *clk;
char *parent_name;
int cpu, ret;
div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
if (!div)
return -ENOMEM;
return ERR_PTR(-ENOMEM);
div->width = 2;
div->shift = 6;
@ -93,43 +105,63 @@ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
if (!init.name)
return -ENOMEM;
return ERR_PTR(-ENOMEM);
init.parent_names = p_names;
p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!p_names[0]) {
kfree(init.name);
return -ENOMEM;
init.parent_data = p_data;
parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!parent_name) {
clk = ERR_PTR(-ENOMEM);
goto err_parent_name;
}
clk = devm_clk_register(dev, &div->hw);
kfree(p_names[0]);
p_data[0].fw_name = parent_name;
p_data[0].name = parent_name;
ret = devm_clk_hw_register(dev, &div->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
clk = &div->hw;
/* clk-krait ignore any rate change if mux is not flagged as enabled */
if (id < 0)
for_each_online_cpu(cpu)
clk_prepare_enable(div->hw.clk);
else
clk_prepare_enable(div->hw.clk);
err_clk:
kfree(parent_name);
err_parent_name:
kfree(init.name);
return PTR_ERR_OR_ZERO(clk);
return clk;
}
static int
static struct clk_hw *
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
int ret;
int cpu, ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
"qsb",
static struct clk_parent_data sec_mux_list[2] = {
{ .name = "qsb", .fw_name = "qsb" },
{},
};
struct clk_init_data init = {
.parent_names = sec_mux_list,
.parent_data = sec_mux_list,
.num_parents = ARRAY_SIZE(sec_mux_list),
.ops = &krait_mux_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
struct clk *clk;
struct clk_hw *clk;
char *parent_name;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return -ENOMEM;
return ERR_PTR(-ENOMEM);
mux->offset = offset;
mux->lpl = id >= 0;
@ -149,44 +181,64 @@ krait_add_sec_mux(struct device *dev, int id, const char *s,
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
return -ENOMEM;
return ERR_PTR(-ENOMEM);
if (unique_aux) {
sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
if (!sec_mux_list[0]) {
parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
if (!parent_name) {
clk = ERR_PTR(-ENOMEM);
goto err_aux;
}
sec_mux_list[1].fw_name = parent_name;
sec_mux_list[1].name = parent_name;
} else {
sec_mux_list[1].name = "apu_aux";
}
clk = devm_clk_register(dev, &mux->hw);
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
ret = krait_notifier_register(dev, clk, mux);
if (ret)
goto unique_aux;
clk = &mux->hw;
unique_aux:
ret = krait_notifier_register(dev, mux->hw.clk, mux);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
/* clk-krait ignore any rate change if mux is not flagged as enabled */
if (id < 0)
for_each_online_cpu(cpu)
clk_prepare_enable(mux->hw.clk);
else
clk_prepare_enable(mux->hw.clk);
err_clk:
if (unique_aux)
kfree(sec_mux_list[0]);
kfree(parent_name);
err_aux:
kfree(init.name);
return PTR_ERR_OR_ZERO(clk);
return clk;
}
static struct clk *
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
static struct clk_hw *
krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
int id, const char *s, unsigned int offset)
{
int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
static struct clk_parent_data p_data[3];
struct clk_init_data init = {
.parent_names = p_names,
.num_parents = ARRAY_SIZE(p_names),
.parent_data = p_data,
.num_parents = ARRAY_SIZE(p_data),
.ops = &krait_mux_clk_ops,
.flags = CLK_SET_RATE_PARENT,
};
struct clk *clk;
struct clk_hw *clk;
char *hfpll_name;
mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
@ -204,48 +256,44 @@ krait_add_pri_mux(struct device *dev, int id, const char *s,
if (!init.name)
return ERR_PTR(-ENOMEM);
p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!p_names[0]) {
hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
if (!hfpll_name) {
clk = ERR_PTR(-ENOMEM);
goto err_p0;
goto err_hfpll;
}
p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
if (!p_names[1]) {
clk = ERR_PTR(-ENOMEM);
goto err_p1;
p_data[0].fw_name = hfpll_name;
p_data[0].name = hfpll_name;
p_data[1].hw = hfpll_div;
p_data[2].hw = sec_mux;
ret = devm_clk_hw_register(dev, &mux->hw);
if (ret) {
clk = ERR_PTR(ret);
goto err_clk;
}
p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!p_names[2]) {
clk = ERR_PTR(-ENOMEM);
goto err_p2;
}
clk = &mux->hw;
clk = devm_clk_register(dev, &mux->hw);
ret = krait_notifier_register(dev, clk, mux);
ret = krait_notifier_register(dev, mux->hw.clk, mux);
if (ret)
goto err_p3;
err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
err_p1:
kfree(p_names[0]);
err_p0:
clk = ERR_PTR(ret);
err_clk:
kfree(hfpll_name);
err_hfpll:
kfree(init.name);
return clk;
}
/* id < 0 for L2, otherwise id == physical CPU number */
static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
{
int ret;
struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
unsigned int offset;
void *p = NULL;
const char *s;
struct clk *clk;
if (id >= 0) {
offset = 0x4501 + (0x1000 * id);
@ -257,22 +305,23 @@ static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
s = "_l2";
}
ret = krait_add_div(dev, id, s, offset);
if (ret) {
clk = ERR_PTR(ret);
hfpll_div = krait_add_div(dev, id, s, offset);
if (IS_ERR(hfpll_div)) {
pri_mux = hfpll_div;
goto err;
}
ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
if (ret) {
clk = ERR_PTR(ret);
sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
if (IS_ERR(sec_mux)) {
pri_mux = sec_mux;
goto err;
}
clk = krait_add_pri_mux(dev, id, s, offset);
pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
err:
kfree(p);
return clk;
return pri_mux;
}
static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
@ -280,7 +329,7 @@ static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
unsigned int idx = clkspec->args[0];
struct clk **clks = data;
if (idx >= 5) {
if (idx >= clks_max) {
pr_err("%s: invalid clock index %d\n", __func__, idx);
return ERR_PTR(-EINVAL);
}
@ -301,9 +350,8 @@ static int krait_cc_probe(struct platform_device *pdev)
const struct of_device_id *id;
unsigned long cur_rate, aux_rate;
int cpu;
struct clk *clk;
struct clk **clks;
struct clk *l2_pri_mux_clk;
struct clk_hw *mux, *l2_pri_mux;
struct clk *clk, **clks;
id = of_match_device(krait_cc_match_table, dev);
if (!id)
@ -322,21 +370,21 @@ static int krait_cc_probe(struct platform_device *pdev)
}
/* Krait configurations have at most 4 CPUs and one L2 */
clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
for_each_possible_cpu(cpu) {
clk = krait_add_clks(dev, cpu, id->data);
mux = krait_add_clks(dev, cpu, id->data);
if (IS_ERR(clk))
return PTR_ERR(clk);
clks[cpu] = clk;
clks[cpu] = mux->clk;
}
l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
if (IS_ERR(l2_pri_mux_clk))
return PTR_ERR(l2_pri_mux_clk);
clks[4] = l2_pri_mux_clk;
l2_pri_mux = krait_add_clks(dev, -1, id->data);
if (IS_ERR(l2_pri_mux))
return PTR_ERR(l2_pri_mux);
clks[l2_mux] = l2_pri_mux->clk;
/*
* We don't want the CPU or L2 clocks to be turned off at late init
@ -346,7 +394,7 @@ static int krait_cc_probe(struct platform_device *pdev)
* they take over.
*/
for_each_online_cpu(cpu) {
clk_prepare_enable(l2_pri_mux_clk);
clk_prepare_enable(clks[l2_mux]);
WARN(clk_prepare_enable(clks[cpu]),
"Unable to turn on CPU%d clock", cpu);
}
@ -362,21 +410,21 @@ static int krait_cc_probe(struct platform_device *pdev)
* two different rates to force a HFPLL reinit under all
* circumstances.
*/
cur_rate = clk_get_rate(l2_pri_mux_clk);
cur_rate = clk_get_rate(clks[l2_mux]);
aux_rate = 384000000;
if (cur_rate == 1) {
pr_info("L2 @ QSB rate. Forcing new rate.\n");
if (cur_rate < aux_rate) {
pr_info("L2 @ Undefined rate. Forcing new rate.\n");
cur_rate = aux_rate;
}
clk_set_rate(l2_pri_mux_clk, aux_rate);
clk_set_rate(l2_pri_mux_clk, 2);
clk_set_rate(l2_pri_mux_clk, cur_rate);
pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
clk_set_rate(clks[l2_mux], aux_rate);
clk_set_rate(clks[l2_mux], 2);
clk_set_rate(clks[l2_mux], cur_rate);
pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
for_each_possible_cpu(cpu) {
clk = clks[cpu];
cur_rate = clk_get_rate(clk);
if (cur_rate == 1) {
pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
if (cur_rate < aux_rate) {
pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
cur_rate = aux_rate;
}

55
drivers/clk/qcom/lpassaudiocc-sc7280.c
View file

@ -722,33 +722,17 @@ static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
};
MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table);
static void lpassaudio_pm_runtime_disable(void *data)
{
pm_runtime_disable(data);
}
static void lpassaudio_pm_clk_destroy(void *data)
{
pm_clk_destroy(data);
}
static int lpassaudio_create_pm_clks(struct platform_device *pdev)
static int lpass_audio_setup_runtime_pm(struct platform_device *pdev)
{
int ret;
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
pm_runtime_enable(&pdev->dev);
ret = devm_add_action_or_reset(&pdev->dev, lpassaudio_pm_runtime_disable, &pdev->dev);
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
return ret;
ret = pm_clk_create(&pdev->dev);
if (ret)
return ret;
ret = devm_add_action_or_reset(&pdev->dev, lpassaudio_pm_clk_destroy, &pdev->dev);
ret = devm_pm_clk_create(&pdev->dev);
if (ret)
return ret;
@ -756,7 +740,7 @@ static int lpassaudio_create_pm_clks(struct platform_device *pdev)
if (ret < 0)
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
return pm_runtime_resume_and_get(&pdev->dev);
}
static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
@ -765,7 +749,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
ret = lpassaudio_create_pm_clks(pdev);
ret = lpass_audio_setup_runtime_pm(pdev);
if (ret)
return ret;
@ -775,8 +759,8 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap)) {
pm_runtime_disable(&pdev->dev);
return PTR_ERR(regmap);
ret = PTR_ERR(regmap);
goto exit;
}
clk_zonda_pll_configure(&lpass_audio_cc_pll, regmap, &lpass_audio_cc_pll_config);
@ -788,20 +772,18 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
pm_runtime_disable(&pdev->dev);
return ret;
goto exit;
}
ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
pm_runtime_disable(&pdev->dev);
return ret;
goto exit;
}
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
return ret;
}
@ -839,14 +821,15 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
ret = lpassaudio_create_pm_clks(pdev);
ret = lpass_audio_setup_runtime_pm(pdev);
if (ret)
return ret;
if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_audio_cc_sc7280_regmap_config.name = "cc";
desc = &lpass_cc_sc7280_desc;
return qcom_cc_probe(pdev, desc);
ret = qcom_cc_probe(pdev, desc);
goto exit;
}
lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";
@ -854,18 +837,22 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
desc = &lpass_aon_cc_sc7280_desc;
regmap = qcom_cc_map(pdev, desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto exit;
}
clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap);
if (ret)
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
goto exit;
}
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
return ret;
}

34
drivers/clk/qcom/lpasscorecc-sc7180.c
View file

@ -356,7 +356,7 @@ static const struct qcom_cc_desc lpass_audio_hm_sc7180_desc = {
.num_gdscs = ARRAY_SIZE(lpass_audio_hm_sc7180_gdscs),
};
static int lpass_create_pm_clks(struct platform_device *pdev)
static int lpass_setup_runtime_pm(struct platform_device *pdev)
{
int ret;
@ -375,7 +375,7 @@ static int lpass_create_pm_clks(struct platform_device *pdev)
if (ret < 0)
dev_err(&pdev->dev, "failed to acquire iface clock\n");
return ret;
return pm_runtime_resume_and_get(&pdev->dev);
}
static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
@ -384,7 +384,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
struct regmap *regmap;
int ret;
ret = lpass_create_pm_clks(pdev);
ret = lpass_setup_runtime_pm(pdev);
if (ret)
return ret;
@ -392,12 +392,14 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
desc = &lpass_audio_hm_sc7180_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);
if (ret)
return ret;
goto exit;
lpass_core_cc_sc7180_regmap_config.name = "lpass_core_cc";
regmap = qcom_cc_map(pdev, &lpass_core_cc_sc7180_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
goto exit;
}
/*
* Keep the CLK always-ON
@ -415,6 +417,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
pm_runtime_mark_last_busy(&pdev->dev);
exit:
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
@ -425,14 +428,19 @@ static int lpass_hm_core_probe(struct platform_device *pdev)
const struct qcom_cc_desc *desc;
int ret;
ret = lpass_create_pm_clks(pdev);
ret = lpass_setup_runtime_pm(pdev);
if (ret)
return ret;
lpass_core_cc_sc7180_regmap_config.name = "lpass_hm_core";
desc = &lpass_core_hm_sc7180_desc;
return qcom_cc_probe_by_index(pdev, 0, desc);
ret = qcom_cc_probe_by_index(pdev, 0, desc);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
return ret;
}
static const struct of_device_id lpass_hm_sc7180_match_table[] = {
@ -451,7 +459,7 @@ static const struct of_device_id lpass_core_cc_sc7180_match_table[] = {
};
MODULE_DEVICE_TABLE(of, lpass_core_cc_sc7180_match_table);
static const struct dev_pm_ops lpass_core_cc_pm_ops = {
static const struct dev_pm_ops lpass_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
@ -460,20 +468,16 @@ static struct platform_driver lpass_core_cc_sc7180_driver = {
.driver = {
.name = "lpass_core_cc-sc7180",
.of_match_table = lpass_core_cc_sc7180_match_table,
.pm = &lpass_core_cc_pm_ops,
.pm = &lpass_pm_ops,
},
};
static const struct dev_pm_ops lpass_hm_pm_ops = {
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
};
static struct platform_driver lpass_hm_sc7180_driver = {
.probe = lpass_hm_core_probe,
.driver = {
.name = "lpass_hm-sc7180",
.of_match_table = lpass_hm_sc7180_match_table,
.pm = &lpass_hm_pm_ops,
.pm = &lpass_pm_ops,
},
};

736
drivers/clk/qcom/mmcc-msm8974.c
View file

File diff suppressed because it is too large Load diff

4
drivers/clk/qcom/reset.c
View file

@ -30,7 +30,7 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = BIT(map->bit);
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, mask);
}
@ -44,7 +44,7 @@ qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
rst = to_qcom_reset_controller(rcdev);
map = &rst->reset_map[id];
mask = BIT(map->bit);
mask = map->bitmask ? map->bitmask : BIT(map->bit);
return regmap_update_bits(rst->regmap, map->reg, mask, 0);
}

1
drivers/clk/qcom/reset.h
View file

@ -12,6 +12,7 @@ struct qcom_reset_map {
unsigned int reg;
u8 bit;
u8 udelay;
u32 bitmask;
};
struct regmap;

100
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h Normal file
View file

@ -0,0 +1,100 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
/* DISPCC clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL1 1
#define DISP_CC_PLL1_OUT_EVEN 2
#define DISP_CC_PLL2 3
#define DISP_CC_MDSS_AHB1_CLK 4
#define DISP_CC_MDSS_AHB_CLK 5
#define DISP_CC_MDSS_AHB_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_CLK 7
#define DISP_CC_MDSS_BYTE0_CLK_SRC 8
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 9
#define DISP_CC_MDSS_BYTE0_INTF_CLK 10
#define DISP_CC_MDSS_BYTE1_CLK 11
#define DISP_CC_MDSS_BYTE1_CLK_SRC 12
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 13
#define DISP_CC_MDSS_BYTE1_INTF_CLK 14
#define DISP_CC_MDSS_DPTX0_AUX_CLK 15
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_CLK 17
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 18
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 20
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 21
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 22
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 23
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 24
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 25
#define DISP_CC_MDSS_DPTX1_AUX_CLK 26
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 27
#define DISP_CC_MDSS_DPTX1_LINK_CLK 28
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 29
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 30
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 32
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 33
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 34
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 35
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 36
#define DISP_CC_MDSS_DPTX2_AUX_CLK 37
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 38
#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_LINK_CLK 49
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54
#define DISP_CC_MDSS_ESC0_CLK 55
#define DISP_CC_MDSS_ESC0_CLK_SRC 56
#define DISP_CC_MDSS_ESC1_CLK 57
#define DISP_CC_MDSS_ESC1_CLK_SRC 58
#define DISP_CC_MDSS_MDP1_CLK 59
#define DISP_CC_MDSS_MDP_CLK 60
#define DISP_CC_MDSS_MDP_CLK_SRC 61
#define DISP_CC_MDSS_MDP_LUT1_CLK 62
#define DISP_CC_MDSS_MDP_LUT_CLK 63
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64
#define DISP_CC_MDSS_PCLK0_CLK 65
#define DISP_CC_MDSS_PCLK0_CLK_SRC 66
#define DISP_CC_MDSS_PCLK1_CLK 67
#define DISP_CC_MDSS_PCLK1_CLK_SRC 68
#define DISP_CC_MDSS_ROT1_CLK 69
#define DISP_CC_MDSS_ROT_CLK 70
#define DISP_CC_MDSS_ROT_CLK_SRC 71
#define DISP_CC_MDSS_RSCC_AHB_CLK 72
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73
#define DISP_CC_MDSS_VSYNC1_CLK 74
#define DISP_CC_MDSS_VSYNC_CLK 75
#define DISP_CC_MDSS_VSYNC_CLK_SRC 76
#define DISP_CC_SLEEP_CLK 77
#define DISP_CC_SLEEP_CLK_SRC 78
#define DISP_CC_XO_CLK 79
#define DISP_CC_XO_CLK_SRC 80
/* DISPCC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_RSCC_BCR 1
/* DISPCC GDSCs */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif

1
include/dt-bindings/clock/qcom,dispcc-sm8250.h
View file

@ -64,6 +64,7 @@
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54
#define DISP_CC_MDSS_EDP_PIXEL_CLK 55
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56
#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57
/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR 0

14
include/dt-bindings/clock/qcom,gcc-ipq8074.h
View file

@ -367,6 +367,20 @@
#define GCC_PCIE1_AHB_ARES 129
#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
#define GCC_PPE_FULL_RESET 132
#define GCC_UNIPHY0_SOFT_RESET 133
#define GCC_UNIPHY0_XPCS_RESET 134
#define GCC_UNIPHY1_SOFT_RESET 135
#define GCC_UNIPHY1_XPCS_RESET 136
#define GCC_UNIPHY2_SOFT_RESET 137
#define GCC_UNIPHY2_XPCS_RESET 138
#define GCC_EDMA_HW_RESET 139
#define GCC_NSSPORT1_RESET 140
#define GCC_NSSPORT2_RESET 141
#define GCC_NSSPORT3_RESET 142
#define GCC_NSSPORT4_RESET 143
#define GCC_NSSPORT5_RESET 144
#define GCC_NSSPORT6_RESET 145
#define USB0_GDSC 0
#define USB1_GDSC 1

Some files were not shown because too many files have changed in this diff Show more