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drm/amdgpu: switch to amdgpu_ras_late_init for gfx v9 block (v2)
call helper function in late init phase to handle ras init for gfx ip block v2: call ras_late_fini to do clean up when fail to enable interrupt Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
b293e891b0
commit
63fa48db49
1 changed files with 22 additions and 72 deletions
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@ -4402,7 +4402,6 @@ static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
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static int gfx_v9_0_ecc_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ras_common_if **ras_if = &adev->gfx.ras_if;
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struct ras_ih_if ih_info = {
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.cb = gfx_v9_0_process_ras_data_cb,
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};
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@ -4410,18 +4409,18 @@ static int gfx_v9_0_ecc_late_init(void *handle)
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.sysfs_name = "gfx_err_count",
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.debugfs_name = "gfx_err_inject",
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};
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struct ras_common_if ras_block = {
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.block = AMDGPU_RAS_BLOCK__GFX,
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.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
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.sub_block_index = 0,
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.name = "gfx",
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};
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int r;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
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amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
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return 0;
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if (!adev->gfx.ras_if) {
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adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->gfx.ras_if)
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return -ENOMEM;
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adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
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adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->gfx.ras_if->sub_block_index = 0;
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strcpy(adev->gfx.ras_if->name, "gfx");
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}
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fs_info.head = ih_info.head = *adev->gfx.ras_if;
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r = gfx_v9_0_do_edc_gds_workarounds(adev);
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if (r)
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@ -4432,71 +4431,22 @@ static int gfx_v9_0_ecc_late_init(void *handle)
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if (r)
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return r;
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/* handle resume path. */
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if (*ras_if) {
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/* resend ras TA enable cmd during resume.
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* prepare to handle failure.
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*/
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ih_info.head = **ras_if;
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r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
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if (r) {
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if (r == -EAGAIN) {
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/* request a gpu reset. will run again. */
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amdgpu_ras_request_reset_on_boot(adev,
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AMDGPU_RAS_BLOCK__GFX);
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return 0;
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}
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/* fail to enable ras, cleanup all. */
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goto irq;
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}
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/* enable successfully. continue. */
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goto resume;
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r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
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&fs_info, &ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
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r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
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if (r)
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goto late_fini;
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}
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*ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL);
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if (!*ras_if)
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return -ENOMEM;
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**ras_if = ras_block;
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r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
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if (r) {
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if (r == -EAGAIN) {
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amdgpu_ras_request_reset_on_boot(adev,
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AMDGPU_RAS_BLOCK__GFX);
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r = 0;
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}
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goto feature;
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}
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ih_info.head = **ras_if;
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fs_info.head = **ras_if;
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r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
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if (r)
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goto interrupt;
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amdgpu_ras_debugfs_create(adev, &fs_info);
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r = amdgpu_ras_sysfs_create(adev, &fs_info);
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if (r)
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goto sysfs;
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resume:
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r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
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if (r)
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goto irq;
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return 0;
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irq:
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amdgpu_ras_sysfs_remove(adev, *ras_if);
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sysfs:
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amdgpu_ras_debugfs_remove(adev, *ras_if);
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amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
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interrupt:
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amdgpu_ras_feature_enable(adev, *ras_if, 0);
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feature:
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kfree(*ras_if);
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*ras_if = NULL;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
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free:
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kfree(adev->gfx.ras_if);
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return r;
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}
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