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drm/bridge: tc358767: increase PLL lock time delay

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The PLL often fails to lock with this delay. The new value was
determined by trial and error increasing the delay bit by bit
until the error did not occurr anymore even after several tries.
Then double that value was taken as the minimum delay to be safe.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # TC9595
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20230721165328.3968759-1-l.stach@pengutronix.de
This commit is contained in:
David Jander 2023-07-21 18:53:27 +02:00 committed by Marek Vasut
parent 4cfe5cc02e
commit 63fbe9db81
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/bridge/tc358767.c
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@ -500,8 +500,8 @@ static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
if (ret)
return ret;
/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
usleep_range(3000, 6000);
/* Wait for PLL to lock: up to 7.5 ms, depending on refclk */
usleep_range(15000, 20000);
return 0;
}