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sata_mv ncq Mask transient IRQs
The chips can handle many transient errors internally without a software IRQ. We now mask/ignore those interrupts here. This is necessary for NCQ, later on. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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3606a38069
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646a4da514
1 changed files with 28 additions and 8 deletions
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@ -170,7 +170,7 @@ enum {
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PCIE_IRQ_CAUSE_OFS = 0x1900,
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PCIE_IRQ_MASK_OFS = 0x1910,
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PCIE_UNMASK_ALL_IRQS = 0x70a, /* assorted bits */
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PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
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HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
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HC_MAIN_IRQ_MASK_OFS = 0x1d64,
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@ -244,14 +244,33 @@ enum {
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EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
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EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
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EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
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EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
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EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
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EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
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EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
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EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
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EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
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EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
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EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
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EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
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EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
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EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
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EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
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EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
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EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
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EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
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EDMA_ERR_OVERRUN_5 = (1 << 5),
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EDMA_ERR_UNDERRUN_5 = (1 << 6),
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EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
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EDMA_ERR_LNK_CTRL_RX_1 |
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EDMA_ERR_LNK_CTRL_RX_3 |
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EDMA_ERR_LNK_CTRL_TX,
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EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
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EDMA_ERR_PRD_PAR |
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EDMA_ERR_DEV_DCON |
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@ -1716,18 +1735,19 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance)
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struct ata_host *host = dev_instance;
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unsigned int hc, handled = 0, n_hcs;
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void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
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u32 irq_stat;
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u32 irq_stat, irq_mask;
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spin_lock(&host->lock);
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irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
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irq_mask = readl(mmio + HC_MAIN_IRQ_MASK_OFS);
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/* check the cases where we either have nothing pending or have read
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* a bogus register value which can indicate HW removal or PCI fault
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*/
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if (!irq_stat || (0xffffffffU == irq_stat))
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return IRQ_NONE;
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if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat))
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goto out_unlock;
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n_hcs = mv_get_hc_count(host->ports[0]->flags);
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spin_lock(&host->lock);
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if (unlikely(irq_stat & PCI_ERR)) {
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mv_pci_error(host, mmio);
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@ -2428,8 +2448,8 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
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writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
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writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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/* unmask all EDMA error interrupts */
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writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
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/* unmask all non-transient EDMA error interrupts */
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writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
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VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
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readl(port_mmio + EDMA_CFG_OFS),
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