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drm/gma500: Add support for SGX interrupts
Add 2D blit status and MMU fault interrupts to the IRQ handler. Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
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parent
b219372dff
commit
64a4aff283
1 changed files with 69 additions and 12 deletions
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@ -200,11 +200,64 @@ static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
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mid_pipe_event_handler(dev, 1);
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}
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/*
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* SGX interrupt handler
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*/
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static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 val, addr;
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int error = false;
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if (stat_1 & _PSB_CE_TWOD_COMPLETE)
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val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
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if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
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val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
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addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
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if (val) {
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if (val & _PSB_CBI_STAT_PF_N_RW)
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DRM_ERROR("SGX MMU page fault:");
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else
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DRM_ERROR("SGX MMU read / write protection fault:");
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if (val & _PSB_CBI_STAT_FAULT_CACHE)
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DRM_ERROR("\tCache requestor");
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if (val & _PSB_CBI_STAT_FAULT_TA)
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DRM_ERROR("\tTA requestor");
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if (val & _PSB_CBI_STAT_FAULT_VDM)
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DRM_ERROR("\tVDM requestor");
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if (val & _PSB_CBI_STAT_FAULT_2D)
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DRM_ERROR("\t2D requestor");
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if (val & _PSB_CBI_STAT_FAULT_PBE)
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DRM_ERROR("\tPBE requestor");
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if (val & _PSB_CBI_STAT_FAULT_TSP)
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DRM_ERROR("\tTSP requestor");
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if (val & _PSB_CBI_STAT_FAULT_ISP)
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DRM_ERROR("\tISP requestor");
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if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
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DRM_ERROR("\tUSSEPDS requestor");
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if (val & _PSB_CBI_STAT_FAULT_HOST)
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DRM_ERROR("\tHost requestor");
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DRM_ERROR("\tMMU failing address is 0x%08x.\n",
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(unsigned int)addr);
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error = true;
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}
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}
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/* Clear bits */
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PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
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PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
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PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
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}
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irqreturn_t psb_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct drm_psb_private *dev_priv = dev->dev_private;
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uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
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u32 sgx_stat_1, sgx_stat_2;
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int handled = 0;
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spin_lock(&dev_priv->irqmask_lock);
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@ -233,14 +286,9 @@ irqreturn_t psb_irq_handler(int irq, void *arg)
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}
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if (sgx_int) {
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/* Not expected - we have it masked, shut it up */
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u32 s, s2;
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s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
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s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
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PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
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PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
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/* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
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we may as well poll even if we add that ! */
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sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
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sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
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psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
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handled = 1;
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}
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@ -269,8 +317,13 @@ void psb_irq_preinstall(struct drm_device *dev)
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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if (gma_power_is_on(dev))
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if (gma_power_is_on(dev)) {
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
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PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
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PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
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PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
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}
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if (dev->vblank[0].enabled)
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dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
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if (dev->vblank[1].enabled)
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@ -286,7 +339,7 @@ void psb_irq_preinstall(struct drm_device *dev)
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/* Revisit this area - want per device masks ? */
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if (dev_priv->ops->hotplug)
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dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
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dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE;
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dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
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/* This register is safe even if display island is off */
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PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
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@ -295,12 +348,16 @@ void psb_irq_preinstall(struct drm_device *dev)
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int psb_irq_postinstall(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *) dev->dev_private;
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
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/* Enable 2D and MMU fault interrupts */
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PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
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PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
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PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
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/* This register is safe even if display island is off */
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PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
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PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
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