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ARM: imx: add suspend in ocram support for i.mx6sl
i.MX6SL's suspend in ocram function is derived from i.MX6Q, it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V, measured on i.MX6SL EVK board, SH5. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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parent
da9e926135
commit
64b0868139
3 changed files with 61 additions and 4 deletions
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@ -105,7 +105,7 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
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AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o
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# i.MX6SL reuses i.MX6Q code
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obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
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obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o
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# i.MX5 based machines
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obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
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@ -121,6 +121,14 @@ static const u32 imx6dl_mmdc_io_offset[] __initconst = {
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0x74c, /* GPR_ADDS */
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};
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static const u32 imx6sl_mmdc_io_offset[] __initconst = {
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0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
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0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
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0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
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0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
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0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
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};
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static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
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.cpu_type = MXC_CPU_IMX6Q,
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.mmdc_compat = "fsl,imx6q-mmdc",
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@ -141,6 +149,16 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
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.mmdc_io_offset = imx6dl_mmdc_io_offset,
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};
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static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
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.cpu_type = MXC_CPU_IMX6SL,
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.mmdc_compat = "fsl,imx6sl-mmdc",
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.src_compat = "fsl,imx6sl-src",
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.iomuxc_compat = "fsl,imx6sl-iomuxc",
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.gpc_compat = "fsl,imx6sl-gpc",
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.mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
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.mmdc_io_offset = imx6sl_mmdc_io_offset,
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};
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/*
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* This structure is for passing necessary data for low level ocram
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* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
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@ -530,5 +548,5 @@ void __init imx6dl_pm_init(void)
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void __init imx6sl_pm_init(void)
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{
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imx6_pm_common_init(NULL);
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imx6_pm_common_init(&imx6sl_pm_data);
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}
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@ -63,6 +63,7 @@
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#define MX6Q_SRC_GPR1 0x20
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#define MX6Q_SRC_GPR2 0x24
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#define MX6Q_MMDC_MAPSR 0x404
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#define MX6Q_MMDC_MPDGCTRL0 0x83c
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#define MX6Q_GPC_IMR1 0x08
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#define MX6Q_GPC_IMR2 0x0c
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#define MX6Q_GPC_IMR3 0x10
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@ -107,14 +108,36 @@
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ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
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ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
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cmp r3, #MXC_CPU_IMX6SL
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bne 4f
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/* reset read FIFO, RST_RD_FIFO */
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ldr r7, =MX6Q_MMDC_MPDGCTRL0
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ldr r6, [r11, r7]
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orr r6, r6, #(1 << 31)
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str r6, [r11, r7]
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2:
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ldr r6, [r11, r7]
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ands r6, r6, #(1 << 31)
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bne 2b
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/* reset FIFO a second time */
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ldr r6, [r11, r7]
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orr r6, r6, #(1 << 31)
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str r6, [r11, r7]
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3:
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ldr r6, [r11, r7]
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ands r6, r6, #(1 << 31)
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bne 3b
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4:
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/* let DDR out of self-refresh */
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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bic r7, r7, #(1 << 21)
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str r7, [r11, #MX6Q_MMDC_MAPSR]
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2:
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5:
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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ands r7, r7, #(1 << 25)
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bne 2b
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bne 5b
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/* enable DDR auto power saving */
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ldr r7, [r11, #MX6Q_MMDC_MAPSR]
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@ -182,12 +205,27 @@ poll_dvfs_set:
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ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
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ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
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add r8, r8, r0
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/* i.MX6SL's last 3 IOs need special setting */
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cmp r3, #MXC_CPU_IMX6SL
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subeq r7, r7, #0x3
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set_mmdc_io_lpm:
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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subs r7, r7, #0x1
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bne set_mmdc_io_lpm
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cmp r3, #MXC_CPU_IMX6SL
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bne set_mmdc_io_lpm_done
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ldr r6, =0x1000
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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ldr r9, [r8], #0x8
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str r6, [r11, r9]
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ldr r6, =0x80000
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ldr r9, [r8]
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str r6, [r11, r9]
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set_mmdc_io_lpm_done:
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/*
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* mask all GPC interrupts before
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* enabling the RBC counters to
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@ -282,6 +320,7 @@ resume:
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str r7, [r11, #MX6Q_SRC_GPR1]
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str r7, [r11, #MX6Q_SRC_GPR2]
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ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET]
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mov r5, #0x1
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resume_mmdc
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