mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

spi: npcm-fiu: Add NPCM8XX support 

Adding FIU NPCM8XX support to NPCM FIU driver.
NPCM8XX FIU supports four controllers.

As part of adding NPCM8XX support:
- Add NPCM8XX specific compatible string.
- Using an internal burst configuration register instead of a GCR
  register.
- Support FIU1 controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Tomer Maimon 2022-07-18 11:11:46 +03:00 committed by Mark Brown
parent d50fef8ae9
commit 650b014fac
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/spi/spi-npcm-fiu.c
View File

@ -36,6 +36,7 @@
#define NPCM_FIU_UMA_DR1 0x34
#define NPCM_FIU_UMA_DR2 0x38
#define NPCM_FIU_UMA_DR3 0x3C
#define NPCM_FIU_CFG 0x78
#define NPCM_FIU_MAX_REG_LIMIT 0x80
/* FIU Direct Read Configuration Register */
@ -151,6 +152,9 @@
#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)
#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)
/* FIU Configuration Register */
#define NPCM_FIU_CFG_FIU_FIX BIT(31)
/* FIU Read Mode */
enum {
DRD_SINGLE_WIRE_MODE = 0,
@ -187,6 +191,7 @@ enum {
FIU0 = 0,
FIU3,
FIUX,
FIU1,
};
struct npcm_fiu_info {
@ -214,6 +219,21 @@ static const struct fiu_data npcm7xx_fiu_data = {
.fiu_max = 3,
};
static const struct npcm_fiu_info npxm8xx_fiu_info[] = {
{.name = "FIU0", .fiu_id = FIU0,
.max_map_size = MAP_SIZE_128MB, .max_cs = 2},
{.name = "FIU3", .fiu_id = FIU3,
.max_map_size = MAP_SIZE_128MB, .max_cs = 4},
{.name = "FIUX", .fiu_id = FIUX,
.max_map_size = MAP_SIZE_16MB, .max_cs = 2},
{.name = "FIU1", .fiu_id = FIU1,
.max_map_size = MAP_SIZE_16MB, .max_cs = 4} };
static const struct fiu_data npxm8xx_fiu_data = {
.npcm_fiu_data_info = npxm8xx_fiu_info,
.fiu_max = 4,
};
struct npcm_fiu_spi;
struct npcm_fiu_chip {
@ -624,6 +644,10 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,
NPCM7XX_INTCR3_FIU_FIX,
NPCM7XX_INTCR3_FIU_FIX);
} else {
regmap_update_bits(fiu->regmap, NPCM_FIU_CFG,
NPCM_FIU_CFG_FIU_FIX,
NPCM_FIU_CFG_FIU_FIX);
}
if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
@ -664,6 +688,7 @@ static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
static const struct of_device_id npcm_fiu_dt_ids[] = {
{ .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data },
{ .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data },
{ /* sentinel */ }
};