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xtensa: rearrange unaligned exception handler
- extract initialization part of the exception handler into a separate function. - use single label for invalid instruction instead of two labels, one for load and one for store, at one place. - use sext instruction for sign extension when available. - store SAR on the stack instead of in a0. - replace numeric labels for load and store writeback with .Lload_w and .Lstore_w respectively. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
3522bcfe1e
commit
651d4aff68
1 changed files with 89 additions and 82 deletions
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@ -157,58 +157,7 @@
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.literal_position
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ENTRY(fast_unaligned)
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/* Note: We don't expect the address to be aligned on a word
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* boundary. After all, the processor generated that exception
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* and it would be a hardware fault.
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*/
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/* Save some working register */
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s32i a4, a2, PT_AREG4
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s32i a5, a2, PT_AREG5
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s32i a6, a2, PT_AREG6
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s32i a7, a2, PT_AREG7
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s32i a8, a2, PT_AREG8
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rsr a0, depc
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s32i a0, a2, PT_AREG2
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s32i a3, a2, PT_AREG3
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rsr a3, excsave1
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movi a4, fast_unaligned_fixup
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s32i a4, a3, EXC_TABLE_FIXUP
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/* Keep value of SAR in a0 */
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rsr a0, sar
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rsr a8, excvaddr # load unaligned memory address
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/* Now, identify one of the following load/store instructions.
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*
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* The only possible danger of a double exception on the
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* following l32i instructions is kernel code in vmalloc
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* memory. The processor was just executing at the EPC_1
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* address, and indeed, already fetched the instruction. That
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* guarantees a TLB mapping, which hasn't been replaced by
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* this unaligned exception handler that uses only static TLB
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* mappings. However, high-level interrupt handlers might
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* modify TLB entries, so for the generic case, we register a
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* TABLE_FIXUP handler here, too.
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*/
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/* a3...a6 saved on stack, a2 = SP */
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/* Extract the instruction that caused the unaligned access. */
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rsr a7, epc1 # load exception address
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movi a3, ~3
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and a3, a3, a7 # mask lower bits
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l32i a4, a3, 0 # load 2 words
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l32i a5, a3, 4
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__ssa8 a7
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__src_b a4, a4, a5 # a4 has the instruction
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call0 .Lsave_and_load_instruction
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/* Analyze the instruction (load or store?). */
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@ -249,7 +198,7 @@ ENTRY(fast_unaligned)
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addi a7, a7, 2 # increment PC (assume 16-bit insn)
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extui a5, a4, INSN_OP0, 4
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_beqi a5, OP0_L32I_N, 1f # l32i.n: jump
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_beqi a5, OP0_L32I_N, .Lload_w# l32i.n: jump
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addi a7, a7, 1
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#else
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@ -257,21 +206,24 @@ ENTRY(fast_unaligned)
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#endif
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extui a5, a4, INSN_OP1, 4
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_beqi a5, OP1_L32I, 1f # l32i: jump
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_beqi a5, OP1_L32I, .Lload_w # l32i: jump
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extui a3, a3, 0, 16 # extract lower 16 bits
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_beqi a5, OP1_L16UI, 1f
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_beqi a5, OP1_L16UI, .Lload_w
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addi a5, a5, -OP1_L16SI
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_bnez a5, .Linvalid_instruction_load
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_bnez a5, .Linvalid_instruction
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/* sign extend value */
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#if XCHAL_HAVE_SEXT
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sext a3, a3, 15
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#else
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slli a3, a3, 16
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srai a3, a3, 16
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#endif
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/* Set target register. */
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1:
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.Lload_w:
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extui a4, a4, INSN_T, 4 # extract target register
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movi a5, .Lload_table
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addx8 a4, a4, a5
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@ -297,28 +249,27 @@ ENTRY(fast_unaligned)
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mov a15, a3 ; _j .Lexit; .align 8
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.Lstore_table:
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l32i a3, a2, PT_AREG0; _j 1f; .align 8
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mov a3, a1; _j 1f; .align 8 # fishy??
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l32i a3, a2, PT_AREG2; _j 1f; .align 8
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l32i a3, a2, PT_AREG3; _j 1f; .align 8
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l32i a3, a2, PT_AREG4; _j 1f; .align 8
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l32i a3, a2, PT_AREG5; _j 1f; .align 8
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l32i a3, a2, PT_AREG6; _j 1f; .align 8
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l32i a3, a2, PT_AREG7; _j 1f; .align 8
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l32i a3, a2, PT_AREG8; _j 1f; .align 8
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mov a3, a9 ; _j 1f; .align 8
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mov a3, a10 ; _j 1f; .align 8
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mov a3, a11 ; _j 1f; .align 8
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mov a3, a12 ; _j 1f; .align 8
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mov a3, a13 ; _j 1f; .align 8
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mov a3, a14 ; _j 1f; .align 8
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mov a3, a15 ; _j 1f; .align 8
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l32i a3, a2, PT_AREG0; _j .Lstore_w; .align 8
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mov a3, a1; _j .Lstore_w; .align 8 # fishy??
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l32i a3, a2, PT_AREG2; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG3; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG4; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG5; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG6; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG7; _j .Lstore_w; .align 8
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l32i a3, a2, PT_AREG8; _j .Lstore_w; .align 8
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mov a3, a9 ; _j .Lstore_w; .align 8
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mov a3, a10 ; _j .Lstore_w; .align 8
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mov a3, a11 ; _j .Lstore_w; .align 8
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mov a3, a12 ; _j .Lstore_w; .align 8
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mov a3, a13 ; _j .Lstore_w; .align 8
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mov a3, a14 ; _j .Lstore_w; .align 8
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mov a3, a15 ; _j .Lstore_w; .align 8
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/* We cannot handle this exception. */
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.extern _kernel_exception
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.Linvalid_instruction_load:
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.Linvalid_instruction_store:
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.Linvalid_instruction:
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movi a4, 0
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rsr a3, excsave1
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@ -326,6 +277,7 @@ ENTRY(fast_unaligned)
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/* Restore a4...a8 and SAR, set SP, and jump to default exception. */
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l32i a0, a2, PT_SAR
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l32i a8, a2, PT_AREG8
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l32i a7, a2, PT_AREG7
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l32i a6, a2, PT_AREG6
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@ -343,8 +295,8 @@ ENTRY(fast_unaligned)
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2: movi a0, _user_exception
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jx a0
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1: # a7: instruction pointer, a4: instruction, a3: value
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# a7: instruction pointer, a4: instruction, a3: value
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.Lstore_w:
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movi a6, 0 # mask: ffffffff:00000000
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#if XCHAL_HAVE_DENSITY
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@ -361,7 +313,7 @@ ENTRY(fast_unaligned)
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extui a5, a4, INSN_OP1, 4 # extract OP1
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_beqi a5, OP1_S32I, 1f # jump if 32 bit store
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_bnei a5, OP1_S16I, .Linvalid_instruction_store
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_bnei a5, OP1_S16I, .Linvalid_instruction
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movi a5, -1
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__extl a3, a3 # get 16-bit value
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@ -434,6 +386,7 @@ ENTRY(fast_unaligned)
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/* Restore working register */
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l32i a0, a2, PT_SAR
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l32i a8, a2, PT_AREG8
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l32i a7, a2, PT_AREG7
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l32i a6, a2, PT_AREG6
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@ -448,6 +401,59 @@ ENTRY(fast_unaligned)
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l32i a2, a2, PT_AREG2
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rfe
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.align 4
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.Lsave_and_load_instruction:
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/* Save some working register */
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s32i a3, a2, PT_AREG3
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s32i a4, a2, PT_AREG4
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s32i a5, a2, PT_AREG5
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s32i a6, a2, PT_AREG6
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s32i a7, a2, PT_AREG7
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s32i a8, a2, PT_AREG8
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rsr a4, depc
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s32i a4, a2, PT_AREG2
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rsr a5, sar
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s32i a5, a2, PT_SAR
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rsr a3, excsave1
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movi a4, fast_unaligned_fixup
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s32i a4, a3, EXC_TABLE_FIXUP
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rsr a8, excvaddr # load unaligned memory address
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/* Now, identify one of the following load/store instructions.
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*
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* The only possible danger of a double exception on the
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* following l32i instructions is kernel code in vmalloc
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* memory. The processor was just executing at the EPC_1
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* address, and indeed, already fetched the instruction. That
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* guarantees a TLB mapping, which hasn't been replaced by
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* this unaligned exception handler that uses only static TLB
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* mappings. However, high-level interrupt handlers might
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* modify TLB entries, so for the generic case, we register a
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* TABLE_FIXUP handler here, too.
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*/
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/* a3...a6 saved on stack, a2 = SP */
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/* Extract the instruction that caused the unaligned access. */
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rsr a7, epc1 # load exception address
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movi a3, ~3
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and a3, a3, a7 # mask lower bits
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l32i a4, a3, 0 # load 2 words
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l32i a5, a3, 4
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__ssa8 a7
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__src_b a4, a4, a5 # a4 has the instruction
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ret
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ENDPROC(fast_unaligned)
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ENTRY(fast_unaligned_fixup)
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@ -459,10 +465,11 @@ ENTRY(fast_unaligned_fixup)
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l32i a7, a2, PT_AREG7
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l32i a6, a2, PT_AREG6
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l32i a5, a2, PT_AREG5
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l32i a4, a2, PT_AREG4
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l32i a4, a2, PT_SAR
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l32i a0, a2, PT_AREG2
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xsr a0, depc # restore depc and a0
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wsr a0, sar
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wsr a4, sar
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wsr a0, depc # restore depc and a0
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l32i a4, a2, PT_AREG4
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rsr a0, exccause
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s32i a0, a2, PT_DEPC # mark as a regular exception
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