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dt-bindings: net: Convert MDIO mux bindings to DT schema
Convert the common MDIO mux bindings to DT schema. Drop the example from mdio-mux.yaml as mdio-mux-gpio.yaml has the same one. Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Andrew Lunn <andrew@lunn.ch> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Russell King <linux@armlinux.org.uk> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210526181411.2888516-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Rob Herring
parent
e9ab77a4f2
commit
652f2efa93
9 changed files with 340 additions and 406 deletions
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@ -17,7 +17,7 @@ Optional properties:
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- clocks: phandle of the core clock which drives the mdio block.
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Additional information regarding generic multiplexer properties can be found
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at- Documentation/devicetree/bindings/net/mdio-mux.txt
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at- Documentation/devicetree/bindings/net/mdio-mux.yaml
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for example:
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@ -1,119 +0,0 @@
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Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
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This is a special case of a MDIO bus multiplexer. One or more GPIO
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lines are used to control which child bus is connected.
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Required properties in addition to the generic multiplexer properties:
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- compatible : mdio-mux-gpio.
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- gpios : GPIO specifiers for each GPIO line. One or more must be specified.
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Example :
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/* The parent MDIO bus. */
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smi1: mdio@1180000001900 {
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compatible = "cavium,octeon-3860-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11800 0x00001900 0x0 0x40>;
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};
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/*
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
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pair of GPIO lines. Child busses 2 and 3 populated with 4
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PHYs each.
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*/
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mdio-mux {
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compatible = "mdio-mux-gpio";
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gpios = <&gpio1 3 0>, <&gpio1 4 0>;
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mdio-parent-bus = <&smi1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy11: ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy12: ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy13: ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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phy14: ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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};
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mdio@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy21: ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy22: ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy23: ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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phy24: ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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};
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135
Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml
Normal file
135
Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml
Normal file
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@ -0,0 +1,135 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description:
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This is a special case of a MDIO bus multiplexer. One or more GPIO
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lines are used to control which child bus is connected.
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allOf:
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- $ref: /schemas/net/mdio-mux.yaml#
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properties:
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compatible:
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const: mdio-mux-gpio
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gpios:
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description:
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List of GPIOs used to control the multiplexer, least significant bit first.
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minItems: 1
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maxItems: 32
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required:
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- compatible
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- gpios
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unevaluatedProperties: false
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examples:
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- |
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/*
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An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
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pair of GPIO lines. Child busses 2 and 3 populated with 4
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PHYs each.
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*/
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mdio-mux {
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compatible = "mdio-mux-gpio";
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gpios = <&gpio1 3 0>, <&gpio1 4 0>;
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mdio-parent-bus = <&smi1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <10 8>; /* Pin 10, active low */
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};
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};
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mdio@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@1 {
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reg = <1>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@2 {
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reg = <2>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@3 {
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reg = <3>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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ethernet-phy@4 {
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reg = <4>;
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marvell,reg-init = <3 0x10 0 0x5777>,
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<3 0x11 0 0x00aa>,
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<3 0x12 0 0x4105>,
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<3 0x13 0 0x0a60>;
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interrupt-parent = <&gpio>;
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interrupts = <12 8>; /* Pin 12, active low */
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};
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};
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};
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...
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@ -1,75 +0,0 @@
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Properties for an MDIO bus multiplexer controlled by a memory-mapped device
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This is a special case of a MDIO bus multiplexer. A memory-mapped device,
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like an FPGA, is used to control which child bus is connected. The mdio-mux
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node must be a child of the memory-mapped device. The driver currently only
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supports devices with 8, 16 or 32-bit registers.
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Required properties in addition to the generic multiplexer properties:
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- compatible : string, must contain "mdio-mux-mmioreg"
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- reg : integer, contains the offset of the register that controls the bus
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multiplexer. The size field in the 'reg' property is the size of
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register, and must therefore be 1, 2, or 4.
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- mux-mask : integer, contains an eight-bit mask that specifies which
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bits in the register control the actual bus multiplexer. The
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'reg' property of each child mdio-mux node must be constrained by
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this mask.
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Example:
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The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
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For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
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A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
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BRDCFG1 that control the actual mux.
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/* The FPGA node */
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fpga: board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x30>;
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ranges = <0 3 0 0x30>;
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mdio-mux-emi2 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&xmdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <9 1>; // BRDCFG1
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mux-mask = <0x6>; // EMI2
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emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2)
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy_xgmii_slot1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1)
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy_xgmii_slot2: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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};
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};
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};
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};
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/* The parent MDIO bus. */
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xmdio0: mdio@f1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-xmdio";
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reg = <0xf1000 0x1000>;
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interrupts = <100 1 0 0>;
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};
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78
Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml
Normal file
78
Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml
Normal file
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@ -0,0 +1,78 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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description: |+
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This is a special case of a MDIO bus multiplexer. A memory-mapped device,
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like an FPGA, is used to control which child bus is connected. The mdio-mux
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node must be a child of the memory-mapped device. The driver currently only
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supports devices with 8, 16 or 32-bit registers.
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allOf:
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- $ref: /schemas/net/mdio-mux.yaml#
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properties:
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compatible:
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items:
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- const: mdio-mux-mmioreg
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- const: mdio-mux
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reg:
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description: Contains the offset of the register that controls the bus
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multiplexer. The size field in the 'reg' property is the size of register,
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and must therefore be 1, 2, or 4.
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maxItems: 1
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mux-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Contains an eight-bit mask that specifies which bits in the
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register control the actual bus multiplexer. The 'reg' property of each
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child mdio-mux node must be constrained by this mask.
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required:
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- compatible
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- reg
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- mux-mask
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unevaluatedProperties: false
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examples:
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- |
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mdio-mux@9 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&xmdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <9 1>; // BRDCFG1
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mux-mask = <0x6>; // EMI2
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mdio@0 { // Slot 1 XAUI (FM2)
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy_xgmii_slot1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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mdio@2 { // Slot 2 XAUI (FM1)
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <4>;
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};
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};
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};
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...
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@ -1,82 +0,0 @@
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Properties for an MDIO bus multiplexer consumer device
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This is a special case of MDIO mux when MDIO mux is defined as a consumer
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of a mux producer device. The mux producer can be of any type like mmio mux
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producer, gpio mux producer or generic register based mux producer.
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Required properties in addition to the MDIO Bus multiplexer properties:
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- compatible : should be "mmio-mux-multiplexer"
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- mux-controls : mux controller node to use for operating the mux
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- mdio-parent-bus : phandle to the parent MDIO bus.
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each child node of mdio bus multiplexer consumer device represent a mdio
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bus.
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for more information please refer
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Documentation/devicetree/bindings/mux/mux-controller.yaml
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and Documentation/devicetree/bindings/net/mdio-mux.txt
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Example:
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In below example the Mux producer and consumer are separate nodes.
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&i2c0 {
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fpga@66 { // fpga connected to i2c
|
||||
compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
|
||||
"simple-mfd";
|
||||
reg = <0x66>;
|
||||
|
||||
mux: mux-controller { // Mux Producer
|
||||
compatible = "reg-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
|
||||
<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio-mux-1 { // Mux consumer
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 0>;
|
||||
mdio-parent-bus = <&emdio1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@8 {
|
||||
reg = <0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
..
|
||||
..
|
||||
};
|
||||
|
||||
mdio-mux-2 { // Mux consumer
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 1>;
|
||||
mdio-parent-bus = <&emdio2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
..
|
||||
..
|
||||
};
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Properties for an MDIO bus multiplexer consumer device
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
|
||||
description: |+
|
||||
This is a special case of MDIO mux when MDIO mux is defined as a consumer
|
||||
of a mux producer device. The mux producer can be of any type like mmio mux
|
||||
producer, gpio mux producer or generic register based mux producer.
|
||||
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/net/mdio-mux.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mdio-mux-multiplexer
|
||||
|
||||
mux-controls:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mux-controls
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mux: mux-controller { // Mux Producer
|
||||
compatible = "reg-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
|
||||
<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
|
||||
};
|
||||
|
||||
mdio-mux-1 { // Mux consumer
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 0>;
|
||||
mdio-parent-bus = <&emdio1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@8 {
|
||||
reg = <0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio-mux-2 { // Mux consumer
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 1>;
|
||||
mdio-parent-bus = <&emdio2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
Common MDIO bus multiplexer/switch properties.
|
||||
|
||||
An MDIO bus multiplexer/switch will have several child busses that are
|
||||
numbered uniquely in a device dependent manner. The nodes for an MDIO
|
||||
bus multiplexer/switch will have one child node for each child bus.
|
||||
|
||||
Required properties:
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
Optional properties:
|
||||
- mdio-parent-bus : phandle to the parent MDIO bus.
|
||||
|
||||
- Other properties specific to the multiplexer/switch hardware.
|
||||
|
||||
Required properties for child nodes:
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- reg : The sub-bus number.
|
||||
|
||||
|
||||
Example :
|
||||
|
||||
/* The parent MDIO bus. */
|
||||
smi1: mdio@1180000001900 {
|
||||
compatible = "cavium,octeon-3860-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x11800 0x00001900 0x0 0x40>;
|
||||
};
|
||||
|
||||
/*
|
||||
An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
|
||||
pair of GPIO lines. Child busses 2 and 3 populated with 4
|
||||
PHYs each.
|
||||
*/
|
||||
mdio-mux {
|
||||
compatible = "mdio-mux-gpio";
|
||||
gpios = <&gpio1 3 0>, <&gpio1 4 0>;
|
||||
mdio-parent-bus = <&smi1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy11: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <10 8>; /* Pin 10, active low */
|
||||
};
|
||||
phy12: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <10 8>; /* Pin 10, active low */
|
||||
};
|
||||
phy13: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <10 8>; /* Pin 10, active low */
|
||||
};
|
||||
phy14: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <10 8>; /* Pin 10, active low */
|
||||
};
|
||||
};
|
||||
|
||||
mdio@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy21: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <12 8>; /* Pin 12, active low */
|
||||
};
|
||||
phy22: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <12 8>; /* Pin 12, active low */
|
||||
};
|
||||
phy23: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <12 8>; /* Pin 12, active low */
|
||||
};
|
||||
phy24: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
marvell,reg-init = <3 0x10 0 0x5777>,
|
||||
<3 0x11 0 0x00aa>,
|
||||
<3 0x12 0 0x4105>,
|
||||
<3 0x13 0 0x0a60>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <12 8>; /* Pin 12, active low */
|
||||
};
|
||||
};
|
||||
};
|
||||
44
Documentation/devicetree/bindings/net/mdio-mux.yaml
Normal file
44
Documentation/devicetree/bindings/net/mdio-mux.yaml
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/mdio-mux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common MDIO bus multiplexer/switch properties.
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
|
||||
description: |+
|
||||
An MDIO bus multiplexer/switch will have several child busses that are
|
||||
numbered uniquely in a device dependent manner. The nodes for an MDIO
|
||||
bus multiplexer/switch will have one child node for each child bus.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^mdio-mux[\-@]?'
|
||||
|
||||
mdio-parent-bus:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
The phandle of the MDIO bus that this multiplexer's master-side port is
|
||||
connected to.
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
'^mdio@[0-9a-f]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: The sub-bus number.
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
Loading…
Reference in a new issue