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clk: samsung: add top clock support for Exynos Auto v9 SoC
This adds support for CMU_TOP which generates clocks for all the function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block and they will generate bus clocks. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
This commit is contained in:
Chanho Park
Sylwester Nawrocki
parent
e61492e478
commit
6587c62f69
2 changed files with 959 additions and 0 deletions
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@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
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obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
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958
drivers/clk/samsung/clk-exynosautov9.c
Normal file
958
drivers/clk/samsung/clk-exynosautov9.c
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@ -0,0 +1,958 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Samsung Electronics Co., Ltd.
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* Author: Chanho Park <chanho61.park@samsung.com>
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*
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* Common Clock Framework support for ExynosAuto V9 SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/samsung,exynosautov9.h>
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#include "clk.h"
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#include "clk-exynos-arm64.h"
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/* ---- CMU_TOP ------------------------------------------------------------ */
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/* Register Offset definitions for CMU_TOP (0x1b240000) */
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#define PLL_LOCKTIME_PLL_SHARED0 0x0000
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#define PLL_LOCKTIME_PLL_SHARED1 0x0004
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#define PLL_LOCKTIME_PLL_SHARED2 0x0008
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#define PLL_LOCKTIME_PLL_SHARED3 0x000c
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#define PLL_LOCKTIME_PLL_SHARED4 0x0010
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#define PLL_CON0_PLL_SHARED0 0x0100
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#define PLL_CON3_PLL_SHARED0 0x010c
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#define PLL_CON0_PLL_SHARED1 0x0140
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#define PLL_CON3_PLL_SHARED1 0x014c
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#define PLL_CON0_PLL_SHARED2 0x0180
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#define PLL_CON3_PLL_SHARED2 0x018c
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#define PLL_CON0_PLL_SHARED3 0x01c0
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#define PLL_CON3_PLL_SHARED3 0x01cc
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#define PLL_CON0_PLL_SHARED4 0x0200
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#define PLL_CON3_PLL_SHARED4 0x020c
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/* MUX */
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#define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
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#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
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#define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
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#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
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#define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
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#define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
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#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
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#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
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#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
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#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
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#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
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#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
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#define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
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#define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
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#define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
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#define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
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#define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
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#define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
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#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
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#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
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#define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
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#define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
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#define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
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#define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
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#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
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#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
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#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
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#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
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#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
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#define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
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#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
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#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
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#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
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#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
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#define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
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#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
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/* DIV */
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#define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
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#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
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#define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
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#define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
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#define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
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#define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
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#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
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#define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
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#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
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#define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
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#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
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#define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
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#define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
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#define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
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#define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
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#define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
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#define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
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#define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
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#define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
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#define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
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#define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
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#define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
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#define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
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#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
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#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
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#define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
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#define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
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#define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
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#define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
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#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
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#define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
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#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
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#define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
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#define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
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#define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
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#define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
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#define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
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#define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
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#define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
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#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
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#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
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#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
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#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
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#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
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#define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
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#define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
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#define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
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#define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
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#define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
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/* GATE */
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#define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
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#define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
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#define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
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#define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
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#define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
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#define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
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#define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
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#define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
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#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
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#define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
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#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
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#define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
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#define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
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#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
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#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
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#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
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#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
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#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
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#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
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#define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
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#define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
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#define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
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#define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
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#define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
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#define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
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#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
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#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
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#define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
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#define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
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#define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
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#define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
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#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
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#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
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#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
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#define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
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#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
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#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
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#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
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#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
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#define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
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static const unsigned long top_clk_regs[] __initconst = {
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PLL_LOCKTIME_PLL_SHARED0,
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PLL_LOCKTIME_PLL_SHARED1,
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PLL_LOCKTIME_PLL_SHARED2,
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PLL_LOCKTIME_PLL_SHARED3,
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PLL_LOCKTIME_PLL_SHARED4,
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PLL_CON0_PLL_SHARED0,
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PLL_CON3_PLL_SHARED0,
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PLL_CON0_PLL_SHARED1,
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PLL_CON3_PLL_SHARED1,
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PLL_CON0_PLL_SHARED2,
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PLL_CON3_PLL_SHARED2,
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PLL_CON0_PLL_SHARED3,
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PLL_CON3_PLL_SHARED3,
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PLL_CON0_PLL_SHARED4,
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PLL_CON3_PLL_SHARED4,
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CLK_CON_MUX_MUX_CLKCMU_ACC_BUS,
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CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
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CLK_CON_MUX_MUX_CLKCMU_AUD_BUS,
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CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
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CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
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CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
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CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
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CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE,
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CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD,
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CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
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CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS,
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CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET,
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CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
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CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
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CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
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CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS,
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CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
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CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
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CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
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CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
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CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
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CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
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CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
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CLK_CON_MUX_MUX_CMU_CMUREF,
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CLK_CON_DIV_CLKCMU_ACC_BUS,
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CLK_CON_DIV_CLKCMU_APM_BUS,
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CLK_CON_DIV_CLKCMU_AUD_BUS,
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CLK_CON_DIV_CLKCMU_AUD_CPU,
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CLK_CON_DIV_CLKCMU_BUSC_BUS,
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CLK_CON_DIV_CLKCMU_BUSMC_BUS,
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CLK_CON_DIV_CLKCMU_CORE_BUS,
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CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
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CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
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CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
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CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
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CLK_CON_DIV_CLKCMU_DPTX_BUS,
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CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
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CLK_CON_DIV_CLKCMU_DPUM_BUS,
|
||||
CLK_CON_DIV_CLKCMU_DPUS0_BUS,
|
||||
CLK_CON_DIV_CLKCMU_DPUS1_BUS,
|
||||
CLK_CON_DIV_CLKCMU_FSYS0_BUS,
|
||||
CLK_CON_DIV_CLKCMU_FSYS0_PCIE,
|
||||
CLK_CON_DIV_CLKCMU_FSYS1_BUS,
|
||||
CLK_CON_DIV_CLKCMU_FSYS1_USBDRD,
|
||||
CLK_CON_DIV_CLKCMU_FSYS2_BUS,
|
||||
CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
|
||||
CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
|
||||
CLK_CON_DIV_CLKCMU_G2D_G2D,
|
||||
CLK_CON_DIV_CLKCMU_G2D_MSCL,
|
||||
CLK_CON_DIV_CLKCMU_G3D00_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_G3D01_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_G3D1_SWITCH,
|
||||
CLK_CON_DIV_CLKCMU_ISPB_BUS,
|
||||
CLK_CON_DIV_CLKCMU_MFC_MFC,
|
||||
CLK_CON_DIV_CLKCMU_MFC_WFD,
|
||||
CLK_CON_DIV_CLKCMU_MIF_BUSP,
|
||||
CLK_CON_DIV_CLKCMU_NPU_BUS,
|
||||
CLK_CON_DIV_CLKCMU_PERIC0_BUS,
|
||||
CLK_CON_DIV_CLKCMU_PERIC0_IP,
|
||||
CLK_CON_DIV_CLKCMU_PERIC1_BUS,
|
||||
CLK_CON_DIV_CLKCMU_PERIC1_IP,
|
||||
CLK_CON_DIV_CLKCMU_PERIS_BUS,
|
||||
CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4,
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV3,
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV4,
|
||||
CLK_CON_DIV_PLL_SHARED4_DIV2,
|
||||
CLK_CON_DIV_PLL_SHARED4_DIV4,
|
||||
CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST,
|
||||
CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST,
|
||||
CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST,
|
||||
CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST,
|
||||
CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST,
|
||||
CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD,
|
||||
CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_ACC_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
|
||||
CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER,
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET,
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
|
||||
CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
|
||||
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD,
|
||||
CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
|
||||
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
|
||||
CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
|
||||
};
|
||||
|
||||
static const struct samsung_pll_clock top_pll_clks[] __initconst = {
|
||||
/* CMU_TOP_PURECLKCOMP */
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared1_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared2_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared3_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
|
||||
PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared4_pll", "oscclk",
|
||||
PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP */
|
||||
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
|
||||
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
|
||||
PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
|
||||
PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
|
||||
PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
|
||||
|
||||
PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
|
||||
PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "dout_shared2_div4" };
|
||||
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "dout_shared0_div3",
|
||||
"dout_shared4_div2", "dout_shared1_div3",
|
||||
"fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_aud_bus_p) = { "dout_shared4_div2", "dout_shared1_div3",
|
||||
"dout_shared2_div3", "dout_shared1_div4" };
|
||||
PNAME(mout_clkcmu_busc_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "dout_shared0_div3",
|
||||
"dout_shared4_div2", "dout_shared1_div3",
|
||||
"dout_shared2_div3", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_cpucl0_switch_p) = {
|
||||
"dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "dout_shared4_div2" };
|
||||
PNAME(mout_clkcmu_cpucl0_cluster_p) = {
|
||||
"fout_shared2_pll", "fout_shared4_pll",
|
||||
"dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "dout_shared4_div2",
|
||||
"dout_shared2_div3", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_dptx_bus_p) = { "dout_shared4_div2", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "dout_shared2_div4" };
|
||||
PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_dpum_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "dout_shared2_div4",
|
||||
"dout_shared4_div4", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_fsys0_bus_p) = {
|
||||
"dout_shared4_div2", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "dout_shared2_div4" };
|
||||
PNAME(mout_clkcmu_fsys0_pcie_p) = { "oscclk", "dout_shared2_div4" };
|
||||
PNAME(mout_clkcmu_fsys1_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_fsys1_usbdrd_p) = {
|
||||
"oscclk", "dout_shared2_div3",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_fsys1_mmc_card_p) = {
|
||||
"oscclk", "dout_shared2_div2",
|
||||
"dout_shared4_div2", "dout_shared2_div3" };
|
||||
PNAME(mout_clkcmu_fsys2_ethernet_p) = {
|
||||
"oscclk", "dout_shared2_div2",
|
||||
"dout_shared0_div3", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_g2d_g2d_p) = { "dout_shared2_div2", "dout_shared0_div3",
|
||||
"dout_shared4_div2", "dout_shared1_div3",
|
||||
"dout_shared2_div3", "dout_shared1_div4",
|
||||
"dout_shared2_div4", "dout_shared4_div4" };
|
||||
PNAME(mout_clkcmu_g3d0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "dout_shared4_div2" };
|
||||
PNAME(mout_clkcmu_g3d1_switch_p) = { "dout_shared2_div2", "dout_shared4_div2",
|
||||
"dout_shared2_div3", "dout_shared1_div4" };
|
||||
PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
|
||||
"fout_shared2_pll", "fout_shared4_pll",
|
||||
"dout_shared0_div2", "dout_shared1_div2",
|
||||
"dout_shared2_div2", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_npu_bus_p) = { "dout_shared1_div2", "dout_shared2_div2",
|
||||
"dout_shared0_div3", "dout_shared4_div2",
|
||||
"dout_shared1_div3", "dout_shared2_div3",
|
||||
"dout_shared1_div4", "fout_shared3_pll" };
|
||||
PNAME(mout_clkcmu_peric0_bus_p) = { "dout_shared2_div3", "dout_shared2_div4" };
|
||||
|
||||
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
|
||||
/* CMU_TOP_PURECLKCOMP */
|
||||
MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
|
||||
PLL_CON0_PLL_SHARED0, 4, 1),
|
||||
MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
|
||||
PLL_CON0_PLL_SHARED1, 4, 1),
|
||||
MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
|
||||
PLL_CON0_PLL_SHARED2, 4, 1),
|
||||
MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
|
||||
PLL_CON0_PLL_SHARED3, 4, 1),
|
||||
MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
|
||||
PLL_CON0_PLL_SHARED4, 4, 1),
|
||||
|
||||
/* BOOST */
|
||||
MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
|
||||
mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
|
||||
MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
|
||||
mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
|
||||
|
||||
/* ACC */
|
||||
MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
|
||||
|
||||
/* APM */
|
||||
MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
|
||||
|
||||
/* AUD */
|
||||
MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
|
||||
MUX(MOUT_CLKCMU_AUD_BUS, "mout_clkcmu_aud_bus", mout_clkcmu_aud_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
|
||||
|
||||
/* BUSC */
|
||||
MUX(MOUT_CLKCMU_BUSC_BUS, "mout_clkcmu_busc_bus",
|
||||
mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
|
||||
|
||||
/* BUSMC */
|
||||
MUX(MOUT_CLKCMU_BUSMC_BUS, "mout_clkcmu_busmc_bus",
|
||||
mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
|
||||
|
||||
/* CORE */
|
||||
MUX(MOUT_CLKCMU_CORE_BUS, "mout_clkcmu_core_bus",
|
||||
mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
|
||||
|
||||
/* CPUCL0 */
|
||||
MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
|
||||
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
|
||||
0, 2),
|
||||
MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
|
||||
mout_clkcmu_cpucl0_cluster_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
|
||||
|
||||
/* CPUCL1 */
|
||||
MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
|
||||
mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
|
||||
0, 2),
|
||||
MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
|
||||
mout_clkcmu_cpucl0_cluster_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
|
||||
|
||||
/* DPTX */
|
||||
MUX(MOUT_CLKCMU_DPTX_BUS, "mout_clkcmu_dptx_bus",
|
||||
mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
|
||||
MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
|
||||
mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
|
||||
|
||||
/* DPUM */
|
||||
MUX(MOUT_CLKCMU_DPUM_BUS, "mout_clkcmu_dpum_bus",
|
||||
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
|
||||
|
||||
/* DPUS */
|
||||
MUX(MOUT_CLKCMU_DPUS0_BUS, "mout_clkcmu_dpus0_bus",
|
||||
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
|
||||
MUX(MOUT_CLKCMU_DPUS1_BUS, "mout_clkcmu_dpus1_bus",
|
||||
mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
|
||||
|
||||
/* FSYS0 */
|
||||
MUX(MOUT_CLKCMU_FSYS0_BUS, "mout_clkcmu_fsys0_bus",
|
||||
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
|
||||
MUX(MOUT_CLKCMU_FSYS0_PCIE, "mout_clkcmu_fsys0_pcie",
|
||||
mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
|
||||
|
||||
/* FSYS1 */
|
||||
MUX(MOUT_CLKCMU_FSYS1_BUS, "mout_clkcmu_fsys1_bus",
|
||||
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
|
||||
MUX(MOUT_CLKCMU_FSYS1_USBDRD, "mout_clkcmu_fsys1_usbdrd",
|
||||
mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD,
|
||||
0, 2),
|
||||
MUX(MOUT_CLKCMU_FSYS1_MMC_CARD, "mout_clkcmu_fsys1_mmc_card",
|
||||
mout_clkcmu_fsys1_mmc_card_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
|
||||
|
||||
/* FSYS2 */
|
||||
MUX(MOUT_CLKCMU_FSYS2_BUS, "mout_clkcmu_fsys2_bus",
|
||||
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
|
||||
MUX(MOUT_CLKCMU_FSYS2_UFS_EMBD, "mout_clkcmu_fsys2_ufs_embd",
|
||||
mout_clkcmu_fsys1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD,
|
||||
0, 2),
|
||||
MUX(MOUT_CLKCMU_FSYS2_ETHERNET, "mout_clkcmu_fsys2_ethernet",
|
||||
mout_clkcmu_fsys2_ethernet_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
|
||||
|
||||
/* G2D */
|
||||
MUX(MOUT_CLKCMU_G2D_G2D, "mout_clkcmu_g2d_g2d", mout_clkcmu_g2d_g2d_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
|
||||
MUX(MOUT_CLKCMU_G2D_MSCL, "mout_clkcmu_g2d_mscl",
|
||||
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
|
||||
|
||||
/* G3D0 */
|
||||
MUX(MOUT_CLKCMU_G3D00_SWITCH, "mout_clkcmu_g3d00_switch",
|
||||
mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH,
|
||||
0, 2),
|
||||
MUX(MOUT_CLKCMU_G3D01_SWITCH, "mout_clkcmu_g3d01_switch",
|
||||
mout_clkcmu_g3d0_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH,
|
||||
0, 2),
|
||||
|
||||
/* G3D1 */
|
||||
MUX(MOUT_CLKCMU_G3D1_SWITCH, "mout_clkcmu_g3d1_switch",
|
||||
mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH,
|
||||
0, 2),
|
||||
|
||||
/* ISPB */
|
||||
MUX(MOUT_CLKCMU_ISPB_BUS, "mout_clkcmu_ispb_bus",
|
||||
mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
|
||||
|
||||
/* MFC */
|
||||
MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
|
||||
mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
|
||||
MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
|
||||
mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
|
||||
|
||||
/* MIF */
|
||||
MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
|
||||
mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
|
||||
MUX(MOUT_CLKCMU_MIF_BUSP, "mout_clkcmu_mif_busp",
|
||||
mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
|
||||
|
||||
/* NPU */
|
||||
MUX(MOUT_CLKCMU_NPU_BUS, "mout_clkcmu_npu_bus", mout_clkcmu_npu_bus_p,
|
||||
CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
|
||||
|
||||
/* PERIC0 */
|
||||
MUX(MOUT_CLKCMU_PERIC0_BUS, "mout_clkcmu_peric0_bus",
|
||||
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
|
||||
MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
|
||||
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
|
||||
|
||||
/* PERIC1 */
|
||||
MUX(MOUT_CLKCMU_PERIC1_BUS, "mout_clkcmu_peric1_bus",
|
||||
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
|
||||
MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
|
||||
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
|
||||
|
||||
/* PERIS */
|
||||
MUX(MOUT_CLKCMU_PERIS_BUS, "mout_clkcmu_peris_bus",
|
||||
mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock top_div_clks[] __initconst = {
|
||||
/* CMU_TOP_PURECLKCOMP */
|
||||
DIV(DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
|
||||
DIV(DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
|
||||
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
|
||||
|
||||
DIV(DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
|
||||
DIV(DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
|
||||
DIV(DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
|
||||
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
|
||||
|
||||
DIV(DOUT_SHARED2_DIV3, "dout_shared2_div3", "mout_shared2_pll",
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
|
||||
DIV(DOUT_SHARED2_DIV2, "dout_shared2_div2", "mout_shared2_pll",
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
|
||||
DIV(DOUT_SHARED2_DIV4, "dout_shared2_div4", "dout_shared2_div2",
|
||||
CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
|
||||
|
||||
DIV(DOUT_SHARED4_DIV2, "dout_shared4_div2", "mout_shared4_pll",
|
||||
CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
|
||||
DIV(DOUT_SHARED4_DIV4, "dout_shared4_div4", "dout_shared4_div2",
|
||||
CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
|
||||
|
||||
/* BOOST */
|
||||
DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
|
||||
"gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
|
||||
|
||||
/* ACC */
|
||||
DIV(DOUT_CLKCMU_ACC_BUS, "dout_clkcmu_acc_bus", "gout_clkcmu_acc_bus",
|
||||
CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
|
||||
|
||||
/* APM */
|
||||
DIV(DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus", "gout_clkcmu_apm_bus",
|
||||
CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
|
||||
|
||||
/* AUD */
|
||||
DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", "gout_clkcmu_aud_cpu",
|
||||
CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
|
||||
DIV(DOUT_CLKCMU_AUD_BUS, "dout_clkcmu_aud_bus", "gout_clkcmu_aud_bus",
|
||||
CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
|
||||
|
||||
/* BUSC */
|
||||
DIV(DOUT_CLKCMU_BUSC_BUS, "dout_clkcmu_busc_bus",
|
||||
"gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
|
||||
|
||||
/* BUSMC */
|
||||
DIV(DOUT_CLKCMU_BUSMC_BUS, "dout_clkcmu_busmc_bus",
|
||||
"gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
|
||||
|
||||
/* CORE */
|
||||
DIV(DOUT_CLKCMU_CORE_BUS, "dout_clkcmu_core_bus",
|
||||
"gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
|
||||
|
||||
/* CPUCL0 */
|
||||
DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
|
||||
"gout_clkcmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
|
||||
0, 3),
|
||||
DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
|
||||
"gout_clkcmu_cpucl0_cluster", CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
|
||||
0, 3),
|
||||
|
||||
/* CPUCL1 */
|
||||
DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
|
||||
"gout_clkcmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
|
||||
0, 3),
|
||||
DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
|
||||
"gout_clkcmu_cpucl1_cluster", CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
|
||||
0, 3),
|
||||
|
||||
/* DPTX */
|
||||
DIV(DOUT_CLKCMU_DPTX_BUS, "dout_clkcmu_dptx_bus",
|
||||
"gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
|
||||
"gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
|
||||
|
||||
/* DPUM */
|
||||
DIV(DOUT_CLKCMU_DPUM_BUS, "dout_clkcmu_dpum_bus",
|
||||
"gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
|
||||
|
||||
/* DPUS */
|
||||
DIV(DOUT_CLKCMU_DPUS0_BUS, "dout_clkcmu_dpus0_bus",
|
||||
"gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_DPUS1_BUS, "dout_clkcmu_dpus1_bus",
|
||||
"gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
|
||||
|
||||
/* FSYS0 */
|
||||
DIV(DOUT_CLKCMU_FSYS0_BUS, "dout_clkcmu_fsys0_bus",
|
||||
"gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
|
||||
|
||||
/* FSYS1 */
|
||||
DIV(DOUT_CLKCMU_FSYS1_BUS, "dout_clkcmu_fsys1_bus",
|
||||
"gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_FSYS1_USBDRD, "dout_clkcmu_fsys1_usbdrd",
|
||||
"gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
|
||||
|
||||
/* FSYS2 */
|
||||
DIV(DOUT_CLKCMU_FSYS2_BUS, "dout_clkcmu_fsys2_bus",
|
||||
"gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_FSYS2_UFS_EMBD, "dout_clkcmu_fsys2_ufs_embd",
|
||||
"gout_clkcmu_fsys2_ufs_embd", CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD,
|
||||
0, 3),
|
||||
DIV(DOUT_CLKCMU_FSYS2_ETHERNET, "dout_clkcmu_fsys2_ethernet",
|
||||
"gout_clkcmu_fsys2_ethernet", CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET,
|
||||
0, 3),
|
||||
|
||||
/* G2D */
|
||||
DIV(DOUT_CLKCMU_G2D_G2D, "dout_clkcmu_g2d_g2d", "gout_clkcmu_g2d_g2d",
|
||||
CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
|
||||
DIV(DOUT_CLKCMU_G2D_MSCL, "dout_clkcmu_g2d_mscl",
|
||||
"gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
|
||||
|
||||
/* G3D0 */
|
||||
DIV(DOUT_CLKCMU_G3D00_SWITCH, "dout_clkcmu_g3d00_switch",
|
||||
"gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
|
||||
DIV(DOUT_CLKCMU_G3D01_SWITCH, "dout_clkcmu_g3d01_switch",
|
||||
"gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
|
||||
|
||||
/* G3D1 */
|
||||
DIV(DOUT_CLKCMU_G3D1_SWITCH, "dout_clkcmu_g3d1_switch",
|
||||
"gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
|
||||
|
||||
/* ISPB */
|
||||
DIV(DOUT_CLKCMU_ISPB_BUS, "dout_clkcmu_ispb_bus",
|
||||
"gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
|
||||
|
||||
/* MFC */
|
||||
DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", "gout_clkcmu_mfc_mfc",
|
||||
CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
|
||||
DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", "gout_clkcmu_mfc_wfd",
|
||||
CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
|
||||
|
||||
/* MIF */
|
||||
DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp",
|
||||
"gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
|
||||
|
||||
/* NPU */
|
||||
DIV(DOUT_CLKCMU_NPU_BUS, "dout_clkcmu_npu_bus", "gout_clkcmu_npu_bus",
|
||||
CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
|
||||
|
||||
/* PERIC0 */
|
||||
DIV(DOUT_CLKCMU_PERIC0_BUS, "dout_clkcmu_peric0_bus",
|
||||
"gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
|
||||
"gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
|
||||
|
||||
/* PERIC1 */
|
||||
DIV(DOUT_CLKCMU_PERIC1_BUS, "dout_clkcmu_peric1_bus",
|
||||
"gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
|
||||
DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
|
||||
"gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
|
||||
|
||||
/* PERIS */
|
||||
DIV(DOUT_CLKCMU_PERIS_BUS, "dout_clkcmu_peris_bus",
|
||||
"gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
|
||||
};
|
||||
|
||||
static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
|
||||
FFACTOR(DOUT_CLKCMU_FSYS0_PCIE, "dout_clkcmu_fsys0_pcie",
|
||||
"gout_clkcmu_fsys0_pcie", 1, 4, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock top_gate_clks[] __initconst = {
|
||||
/* BOOST */
|
||||
GATE(GOUT_CLKCMU_CMU_BOOST, "gout_clkcmu_cmu_boost",
|
||||
"mout_clkcmu_cmu_boost", CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
|
||||
21, 0, 0),
|
||||
|
||||
GATE(GOUT_CLKCMU_CPUCL0_BOOST, "gout_clkcmu_cpucl0_boost",
|
||||
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_CPUCL1_BOOST, "gout_clkcmu_cpucl1_boost",
|
||||
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_CORE_BOOST, "gout_clkcmu_core_boost",
|
||||
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_BUSC_BOOST, "gout_clkcmu_busc_boost",
|
||||
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
|
||||
|
||||
GATE(GOUT_CLKCMU_BUSMC_BOOST, "gout_clkcmu_busmc_boost",
|
||||
"dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_MIF_BOOST, "gout_clkcmu_mif_boost", "dout_cmu_boost",
|
||||
CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
|
||||
|
||||
/* ACC */
|
||||
GATE(GOUT_CLKCMU_ACC_BUS, "gout_clkcmu_acc_bus", "mout_clkcmu_acc_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
|
||||
|
||||
/* APM */
|
||||
GATE(GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus", "mout_clkcmu_apm_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* AUD */
|
||||
GATE(GOUT_CLKCMU_AUD_CPU, "gout_clkcmu_aud_cpu", "mout_clkcmu_aud_cpu",
|
||||
CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_AUD_BUS, "gout_clkcmu_aud_bus", "mout_clkcmu_aud_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
|
||||
|
||||
/* BUSC */
|
||||
GATE(GOUT_CLKCMU_BUSC_BUS, "gout_clkcmu_busc_bus",
|
||||
"mout_clkcmu_busc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 21,
|
||||
CLK_IS_CRITICAL, 0),
|
||||
|
||||
/* BUSMC */
|
||||
GATE(GOUT_CLKCMU_BUSMC_BUS, "gout_clkcmu_busmc_bus",
|
||||
"mout_clkcmu_busmc_bus", CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS, 21,
|
||||
CLK_IS_CRITICAL, 0),
|
||||
|
||||
/* CORE */
|
||||
GATE(GOUT_CLKCMU_CORE_BUS, "gout_clkcmu_core_bus",
|
||||
"mout_clkcmu_core_bus", CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
|
||||
21, 0, 0),
|
||||
|
||||
/* CPUCL0 */
|
||||
GATE(GOUT_CLKCMU_CPUCL0_SWITCH, "gout_clkcmu_cpucl0_switch",
|
||||
"mout_clkcmu_cpucl0_switch",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(GOUT_CLKCMU_CPUCL0_CLUSTER, "gout_clkcmu_cpucl0_cluster",
|
||||
"mout_clkcmu_cpucl0_cluster",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* CPUCL1 */
|
||||
GATE(GOUT_CLKCMU_CPUCL1_SWITCH, "gout_clkcmu_cpucl1_switch",
|
||||
"mout_clkcmu_cpucl1_switch",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(GOUT_CLKCMU_CPUCL1_CLUSTER, "gout_clkcmu_cpucl1_cluster",
|
||||
"mout_clkcmu_cpucl1_cluster",
|
||||
CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* DPTX */
|
||||
GATE(GOUT_CLKCMU_DPTX_BUS, "gout_clkcmu_dptx_bus",
|
||||
"mout_clkcmu_dptx_bus", CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_DPTX_DPGTC, "gout_clkcmu_dptx_dpgtc",
|
||||
"mout_clkcmu_dptx_dpgtc", CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC,
|
||||
21, 0, 0),
|
||||
|
||||
/* DPUM */
|
||||
GATE(GOUT_CLKCMU_DPUM_BUS, "gout_clkcmu_dpum_bus",
|
||||
"mout_clkcmu_dpum_bus", CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS,
|
||||
21, 0, 0),
|
||||
|
||||
/* DPUS */
|
||||
GATE(GOUT_CLKCMU_DPUS0_BUS, "gout_clkcmu_dpus0_bus",
|
||||
"mout_clkcmu_dpus0_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_DPUS1_BUS, "gout_clkcmu_dpus1_bus",
|
||||
"mout_clkcmu_dpus1_bus", CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS,
|
||||
21, 0, 0),
|
||||
|
||||
/* FSYS0 */
|
||||
GATE(GOUT_CLKCMU_FSYS0_BUS, "gout_clkcmu_fsys0_bus",
|
||||
"mout_clkcmu_fsys0_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_FSYS0_PCIE, "gout_clkcmu_fsys0_pcie",
|
||||
"mout_clkcmu_fsys0_pcie", CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE,
|
||||
21, 0, 0),
|
||||
|
||||
/* FSYS1 */
|
||||
GATE(GOUT_CLKCMU_FSYS1_BUS, "gout_clkcmu_fsys1_bus",
|
||||
"mout_clkcmu_fsys1_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_FSYS1_USBDRD, "gout_clkcmu_fsys1_usbdrd",
|
||||
"mout_clkcmu_fsys1_usbdrd", CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_FSYS1_MMC_CARD, "gout_clkcmu_fsys1_mmc_card",
|
||||
"mout_clkcmu_fsys1_mmc_card",
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
|
||||
|
||||
/* FSYS2 */
|
||||
GATE(GOUT_CLKCMU_FSYS2_BUS, "gout_clkcmu_fsys2_bus",
|
||||
"mout_clkcmu_fsys2_bus", CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_FSYS2_UFS_EMBD, "gout_clkcmu_fsys2_ufs_embd",
|
||||
"mout_clkcmu_fsys2_ufs_embd",
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_FSYS2_ETHERNET, "gout_clkcmu_fsys2_ethernet",
|
||||
"mout_clkcmu_fsys2_ethernet",
|
||||
CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
|
||||
|
||||
/* G2D */
|
||||
GATE(GOUT_CLKCMU_G2D_G2D, "gout_clkcmu_g2d_g2d",
|
||||
"mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_G2D_MSCL, "gout_clkcmu_g2d_mscl",
|
||||
"mout_clkcmu_g2d_mscl", CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
|
||||
21, 0, 0),
|
||||
|
||||
/* G3D0 */
|
||||
GATE(GOUT_CLKCMU_G3D00_SWITCH, "gout_clkcmu_g3d00_switch",
|
||||
"mout_clkcmu_g3d00_switch", CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_G3D01_SWITCH, "gout_clkcmu_g3d01_switch",
|
||||
"mout_clkcmu_g3d01_switch", CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH,
|
||||
21, 0, 0),
|
||||
|
||||
/* G3D1 */
|
||||
GATE(GOUT_CLKCMU_G3D1_SWITCH, "gout_clkcmu_g3d1_switch",
|
||||
"mout_clkcmu_g3d1_switch", CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH,
|
||||
21, 0, 0),
|
||||
|
||||
/* ISPB */
|
||||
GATE(GOUT_CLKCMU_ISPB_BUS, "gout_clkcmu_ispb_bus",
|
||||
"mout_clkcmu_ispb_bus", CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS,
|
||||
21, 0, 0),
|
||||
|
||||
/* MFC */
|
||||
GATE(GOUT_CLKCMU_MFC_MFC, "gout_clkcmu_mfc_mfc", "mout_clkcmu_mfc_mfc",
|
||||
CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_MFC_WFD, "gout_clkcmu_mfc_wfd", "mout_clkcmu_mfc_wfd",
|
||||
CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
|
||||
|
||||
/* MIF */
|
||||
GATE(GOUT_CLKCMU_MIF_SWITCH, "gout_clkcmu_mif_switch",
|
||||
"mout_clkcmu_mif_switch", CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(GOUT_CLKCMU_MIF_BUSP, "gout_clkcmu_mif_busp",
|
||||
"mout_clkcmu_mif_busp", CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
|
||||
/* NPU */
|
||||
GATE(GOUT_CLKCMU_NPU_BUS, "gout_clkcmu_npu_bus", "mout_clkcmu_npu_bus",
|
||||
CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
|
||||
|
||||
/* PERIC0 */
|
||||
GATE(GOUT_CLKCMU_PERIC0_BUS, "gout_clkcmu_peric0_bus",
|
||||
"mout_clkcmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_PERIC0_IP, "gout_clkcmu_peric0_ip",
|
||||
"mout_clkcmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
|
||||
21, 0, 0),
|
||||
|
||||
/* PERIC1 */
|
||||
GATE(GOUT_CLKCMU_PERIC1_BUS, "gout_clkcmu_peric1_bus",
|
||||
"mout_clkcmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
|
||||
21, 0, 0),
|
||||
GATE(GOUT_CLKCMU_PERIC1_IP, "gout_clkcmu_peric1_ip",
|
||||
"mout_clkcmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
|
||||
21, 0, 0),
|
||||
|
||||
/* PERIS */
|
||||
GATE(GOUT_CLKCMU_PERIS_BUS, "gout_clkcmu_peris_bus",
|
||||
"mout_clkcmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
|
||||
21, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info top_cmu_info __initconst = {
|
||||
.pll_clks = top_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(top_pll_clks),
|
||||
.mux_clks = top_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(top_mux_clks),
|
||||
.div_clks = top_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(top_div_clks),
|
||||
.fixed_factor_clks = top_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
|
||||
.gate_clks = top_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
|
||||
.nr_clk_ids = TOP_NR_CLK,
|
||||
.clk_regs = top_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynosautov9_cmu_top_init(struct device_node *np)
|
||||
{
|
||||
exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
|
||||
}
|
||||
|
||||
/* Register CMU_TOP early, as it's a dependency for other early domains */
|
||||
CLK_OF_DECLARE(exynosautov9_cmu_top, "samsung,exynosautov9-cmu-top",
|
||||
exynosautov9_cmu_top_init);
|
||||
Loading…
Reference in a new issue