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dt-bindings: interconnect: Add Qualcomm SM6115 NoC
Add bindings for Qualcomm SM6115 Network-On-Chip interconnect. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231125-topic-6115icc-v3-1-bd8907b8cfd7@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
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Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml
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Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM6115 Network-On-Chip interconnect
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maintainers:
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- Konrad Dybcio <konradybcio@kernel.org>
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description:
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The Qualcomm SM6115 interconnect providers support adjusting the
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bandwidth requirements between the various NoC fabrics.
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properties:
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compatible:
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enum:
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- qcom,sm6115-bimc
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- qcom,sm6115-cnoc
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- qcom,sm6115-snoc
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 4
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clock-names:
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minItems: 1
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maxItems: 4
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# Child node's properties
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patternProperties:
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'^interconnect-[a-z0-9]+$':
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type: object
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description:
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The interconnect providers do not have a separate QoS register space,
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but share parent's space.
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$ref: qcom,rpm-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,sm6115-clk-virt
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- qcom,sm6115-mmrt-virt
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- qcom,sm6115-mmnrt-virt
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required:
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- compatible
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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allOf:
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- $ref: qcom,rpm-common.yaml#
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- if:
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properties:
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compatible:
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const: qcom,sm6115-cnoc
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then:
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properties:
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clocks:
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items:
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- description: USB-NoC AXI clock
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clock-names:
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items:
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- const: usb_axi
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- if:
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properties:
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compatible:
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const: qcom,sm6115-snoc
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then:
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properties:
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clocks:
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items:
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- description: CPU-NoC AXI clock.
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- description: UFS-NoC AXI clock.
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- description: USB-NoC AXI clock.
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- description: IPA clock.
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clock-names:
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items:
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- const: cpu_axi
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- const: ufs_axi
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- const: usb_axi
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- const: ipa
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- if:
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properties:
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compatible:
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enum:
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- qcom,sm6115-bimc
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- qcom,sm6115-clk-virt
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- qcom,sm6115-mmrt-virt
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- qcom,sm6115-mmnrt-virt
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then:
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properties:
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clocks: false
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clock-names: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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snoc: interconnect@1880000 {
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compatible = "qcom,sm6115-snoc";
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reg = <0x01880000 0x60200>;
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clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
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<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
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<&rpmcc RPM_SMD_IPA_CLK>;
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clock-names = "cpu_axi",
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"ufs_axi",
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"usb_axi",
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"ipa";
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#interconnect-cells = <1>;
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qup_virt: interconnect-clk {
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compatible = "qcom,sm6115-clk-virt";
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#interconnect-cells = <1>;
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};
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mmnrt_virt: interconnect-mmnrt {
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compatible = "qcom,sm6115-mmnrt-virt";
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#interconnect-cells = <1>;
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};
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mmrt_virt: interconnect-mmrt {
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compatible = "qcom,sm6115-mmrt-virt";
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#interconnect-cells = <1>;
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};
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};
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cnoc: interconnect@1900000 {
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compatible = "qcom,sm6115-cnoc";
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reg = <0x01900000 0x8200>;
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#interconnect-cells = <1>;
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};
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111
include/dt-bindings/interconnect/qcom,sm6115.h
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include/dt-bindings/interconnect/qcom,sm6115.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H
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/* BIMC */
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#define MASTER_AMPSS_M0 0
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#define MASTER_SNOC_BIMC_RT 1
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#define MASTER_SNOC_BIMC_NRT 2
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#define SNOC_BIMC_MAS 3
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#define MASTER_GRAPHICS_3D 4
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#define MASTER_TCU_0 5
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#define SLAVE_EBI_CH0 6
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#define BIMC_SNOC_SLV 7
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/* CNOC */
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#define SNOC_CNOC_MAS 0
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#define MASTER_QDSS_DAP 1
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#define SLAVE_AHB2PHY_USB 2
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#define SLAVE_APSS_THROTTLE_CFG 3
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#define SLAVE_BIMC_CFG 4
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#define SLAVE_BOOT_ROM 5
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#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
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#define SLAVE_CAMERA_RT_THROTTLE_CFG 7
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#define SLAVE_CAMERA_CFG 8
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#define SLAVE_CLK_CTL 9
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#define SLAVE_RBCPR_CX_CFG 10
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#define SLAVE_RBCPR_MX_CFG 11
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#define SLAVE_CRYPTO_0_CFG 12
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#define SLAVE_DCC_CFG 13
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#define SLAVE_DDR_PHY_CFG 14
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#define SLAVE_DDR_SS_CFG 15
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#define SLAVE_DISPLAY_CFG 16
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#define SLAVE_DISPLAY_THROTTLE_CFG 17
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#define SLAVE_GPU_CFG 18
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#define SLAVE_GPU_THROTTLE_CFG 19
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#define SLAVE_HWKM_CORE 20
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#define SLAVE_IMEM_CFG 21
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#define SLAVE_IPA_CFG 22
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#define SLAVE_LPASS 23
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#define SLAVE_MAPSS 24
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#define SLAVE_MDSP_MPU_CFG 25
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#define SLAVE_MESSAGE_RAM 26
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#define SLAVE_CNOC_MSS 27
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#define SLAVE_PDM 28
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#define SLAVE_PIMEM_CFG 29
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#define SLAVE_PKA_CORE 30
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#define SLAVE_PMIC_ARB 31
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#define SLAVE_QDSS_CFG 32
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#define SLAVE_QM_CFG 33
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#define SLAVE_QM_MPU_CFG 34
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#define SLAVE_QPIC 35
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#define SLAVE_QUP_0 36
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#define SLAVE_RPM 37
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#define SLAVE_SDCC_1 38
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#define SLAVE_SDCC_2 39
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#define SLAVE_SECURITY 40
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#define SLAVE_SNOC_CFG 41
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#define SLAVE_TCSR 42
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#define SLAVE_TLMM 43
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#define SLAVE_USB3 44
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#define SLAVE_VENUS_CFG 45
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#define SLAVE_VENUS_THROTTLE_CFG 46
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#define SLAVE_VSENSE_CTRL_CFG 47
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#define SLAVE_SERVICE_CNOC 48
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/* SNOC */
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#define MASTER_CRYPTO_CORE0 0
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#define MASTER_SNOC_CFG 1
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#define MASTER_TIC 2
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#define MASTER_ANOC_SNOC 3
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#define BIMC_SNOC_MAS 4
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#define MASTER_PIMEM 5
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#define MASTER_QDSS_BAM 6
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#define MASTER_QPIC 7
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#define MASTER_QUP_0 8
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#define MASTER_IPA 9
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#define MASTER_QDSS_ETR 10
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#define MASTER_SDCC_1 11
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#define MASTER_SDCC_2 12
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#define MASTER_USB3 13
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#define SLAVE_APPSS 14
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#define SNOC_CNOC_SLV 15
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#define SLAVE_OCIMEM 16
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#define SLAVE_PIMEM 17
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#define SNOC_BIMC_SLV 18
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#define SLAVE_SERVICE_SNOC 19
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#define SLAVE_QDSS_STM 20
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#define SLAVE_TCU 21
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#define SLAVE_ANOC_SNOC 22
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/* CLK Virtual */
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#define MASTER_QUP_CORE_0 0
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#define SLAVE_QUP_CORE_0 1
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/* MMRT Virtual */
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#define MASTER_CAMNOC_HF 0
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#define MASTER_MDP_PORT0 1
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#define SLAVE_SNOC_BIMC_RT 2
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/* MMNRT Virtual */
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#define MASTER_CAMNOC_SF 0
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#define MASTER_VIDEO_P0 1
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#define MASTER_VIDEO_PROC 2
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#define SLAVE_SNOC_BIMC_NRT 3
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#endif
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