drm/radeon/kms: add dpm support for btc (v3)
This adds dpm support for btc asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching (requires additional acpi support) Set radeon.dpm=1 to enable. v2: reduce stack usage v3: attempt to fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
dc50ba7f9a
commit
6596afd48a
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@ -78,7 +78,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
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si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
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r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
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rv770_smc.o cypress_dpm.o
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rv770_smc.o cypress_dpm.o btc_dpm.o
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,32 @@
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __BTC_DPM_H__
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#define __BTC_DPM_H__
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#define BARTS_MGCGCGTSSMCTRL_DFLT 0x81944000
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#define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e944000
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#define CAICOS_MGCGCGTSSMCTRL_DFLT 0x46944040
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#define BTC_CGULVPARAMETER_DFLT 0x00040035
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#define BTC_CGULVCONTROL_DFLT 0x00001450
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#endif
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@ -0,0 +1,181 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef _BTCD_H_
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#define _BTCD_H_
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/* pm registers */
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#define GENERAL_PWRMGT 0x63c
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# define GLOBAL_PWRMGT_EN (1 << 0)
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# define STATIC_PM_EN (1 << 1)
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# define THERMAL_PROTECTION_DIS (1 << 2)
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# define THERMAL_PROTECTION_TYPE (1 << 3)
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# define ENABLE_GEN2PCIE (1 << 4)
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# define ENABLE_GEN2XSP (1 << 5)
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# define SW_SMIO_INDEX(x) ((x) << 6)
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# define SW_SMIO_INDEX_MASK (3 << 6)
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# define SW_SMIO_INDEX_SHIFT 6
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# define LOW_VOLT_D2_ACPI (1 << 8)
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# define LOW_VOLT_D3_ACPI (1 << 9)
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# define VOLT_PWRMGT_EN (1 << 10)
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# define BACKBIAS_PAD_EN (1 << 18)
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# define BACKBIAS_VALUE (1 << 19)
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# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
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# define AC_DC_SW (1 << 24)
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#define CG_BIF_REQ_AND_RSP 0x7f4
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#define CG_CLIENT_REQ(x) ((x) << 0)
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#define CG_CLIENT_REQ_MASK (0xff << 0)
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#define CG_CLIENT_REQ_SHIFT 0
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#define CG_CLIENT_RESP(x) ((x) << 8)
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#define CG_CLIENT_RESP_MASK (0xff << 8)
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#define CG_CLIENT_RESP_SHIFT 8
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#define CLIENT_CG_REQ(x) ((x) << 16)
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#define CLIENT_CG_REQ_MASK (0xff << 16)
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#define CLIENT_CG_REQ_SHIFT 16
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#define CLIENT_CG_RESP(x) ((x) << 24)
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#define CLIENT_CG_RESP_MASK (0xff << 24)
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#define CLIENT_CG_RESP_SHIFT 24
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#define SCLK_PSKIP_CNTL 0x8c0
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#define PSKIP_ON_ALLOW_STOP_HI(x) ((x) << 16)
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#define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16)
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#define PSKIP_ON_ALLOW_STOP_HI_SHIFT 16
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#define CG_ULV_CONTROL 0x8c8
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#define CG_ULV_PARAMETER 0x8cc
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#define MC_ARB_DRAM_TIMING 0x2774
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#define MC_ARB_DRAM_TIMING2 0x2778
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#define MC_ARB_RFSH_RATE 0x27b0
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#define POWERMODE0(x) ((x) << 0)
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#define POWERMODE0_MASK (0xff << 0)
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#define POWERMODE0_SHIFT 0
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#define POWERMODE1(x) ((x) << 8)
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#define POWERMODE1_MASK (0xff << 8)
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#define POWERMODE1_SHIFT 8
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#define POWERMODE2(x) ((x) << 16)
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#define POWERMODE2_MASK (0xff << 16)
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#define POWERMODE2_SHIFT 16
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#define POWERMODE3(x) ((x) << 24)
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#define POWERMODE3_MASK (0xff << 24)
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#define POWERMODE3_SHIFT 24
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#define MC_ARB_BURST_TIME 0x2808
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#define STATE0(x) ((x) << 0)
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#define STATE0_MASK (0x1f << 0)
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#define STATE0_SHIFT 0
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#define STATE1(x) ((x) << 5)
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#define STATE1_MASK (0x1f << 5)
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#define STATE1_SHIFT 5
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#define STATE2(x) ((x) << 10)
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#define STATE2_MASK (0x1f << 10)
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#define STATE2_SHIFT 10
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#define STATE3(x) ((x) << 15)
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#define STATE3_MASK (0x1f << 15)
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#define STATE3_SHIFT 15
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#define MC_SEQ_RAS_TIMING 0x28a0
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#define MC_SEQ_CAS_TIMING 0x28a4
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#define MC_SEQ_MISC_TIMING 0x28a8
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#define MC_SEQ_MISC_TIMING2 0x28ac
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#define MC_SEQ_RD_CTL_D0 0x28b4
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#define MC_SEQ_RD_CTL_D1 0x28b8
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#define MC_SEQ_WR_CTL_D0 0x28bc
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#define MC_SEQ_WR_CTL_D1 0x28c0
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#define MC_PMG_AUTO_CFG 0x28d4
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#define MC_SEQ_STATUS_M 0x29f4
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# define PMG_PWRSTATE (1 << 16)
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#define MC_SEQ_MISC0 0x2a00
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#define MC_SEQ_MISC0_GDDR5_SHIFT 28
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#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
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#define MC_SEQ_MISC0_GDDR5_VALUE 5
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#define MC_SEQ_MISC1 0x2a04
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#define MC_SEQ_RESERVE_M 0x2a08
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#define MC_PMG_CMD_EMRS 0x2a0c
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#define MC_SEQ_MISC3 0x2a2c
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#define MC_SEQ_MISC5 0x2a54
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#define MC_SEQ_MISC6 0x2a58
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#define MC_SEQ_MISC7 0x2a64
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#define MC_SEQ_CG 0x2a68
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#define CG_SEQ_REQ(x) ((x) << 0)
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#define CG_SEQ_REQ_MASK (0xff << 0)
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#define CG_SEQ_REQ_SHIFT 0
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#define CG_SEQ_RESP(x) ((x) << 8)
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#define CG_SEQ_RESP_MASK (0xff << 8)
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#define CG_SEQ_RESP_SHIFT 8
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#define SEQ_CG_REQ(x) ((x) << 16)
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#define SEQ_CG_REQ_MASK (0xff << 16)
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#define SEQ_CG_REQ_SHIFT 16
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#define SEQ_CG_RESP(x) ((x) << 24)
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#define SEQ_CG_RESP_MASK (0xff << 24)
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#define SEQ_CG_RESP_SHIFT 24
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#define MC_SEQ_RAS_TIMING_LP 0x2a6c
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#define MC_SEQ_CAS_TIMING_LP 0x2a70
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#define MC_SEQ_MISC_TIMING_LP 0x2a74
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#define MC_SEQ_MISC_TIMING2_LP 0x2a78
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#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
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#define MC_SEQ_WR_CTL_D1_LP 0x2a80
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#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
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#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
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#define MC_PMG_CMD_MRS 0x2aac
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#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
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#define MC_SEQ_RD_CTL_D1_LP 0x2b20
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#define MC_PMG_CMD_MRS1 0x2b44
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#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
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#define LB_SYNC_RESET_SEL 0x6b28
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#define LB_SYNC_RESET_SEL_MASK (3 << 0)
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#define LB_SYNC_RESET_SEL_SHIFT 0
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/* PCIE link stuff */
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#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
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# define LC_GEN2_EN_STRAP (1 << 0)
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# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
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# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
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# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
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# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
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# define LC_CURRENT_DATA_RATE (1 << 11)
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# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
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# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
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# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
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# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
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# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
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# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
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# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
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#endif
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@ -180,13 +180,16 @@ extern int sumo_rlc_init(struct radeon_device *rdev);
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MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
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MODULE_FIRMWARE("radeon/BARTS_me.bin");
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MODULE_FIRMWARE("radeon/BARTS_mc.bin");
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MODULE_FIRMWARE("radeon/BARTS_smc.bin");
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MODULE_FIRMWARE("radeon/BTC_rlc.bin");
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MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
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MODULE_FIRMWARE("radeon/TURKS_me.bin");
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MODULE_FIRMWARE("radeon/TURKS_mc.bin");
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MODULE_FIRMWARE("radeon/TURKS_smc.bin");
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MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
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MODULE_FIRMWARE("radeon/CAICOS_me.bin");
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MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
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MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
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MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
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@ -683,6 +686,7 @@ int ni_init_microcode(struct radeon_device *rdev)
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const char *chip_name;
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const char *rlc_chip_name;
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size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
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size_t smc_req_size = 0;
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char fw_name[30];
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int err;
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@ -703,6 +707,7 @@ int ni_init_microcode(struct radeon_device *rdev)
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me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
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rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
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mc_req_size = BTC_MC_UCODE_SIZE * 4;
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smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
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break;
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case CHIP_TURKS:
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chip_name = "TURKS";
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@ -711,6 +716,7 @@ int ni_init_microcode(struct radeon_device *rdev)
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me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
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rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
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mc_req_size = BTC_MC_UCODE_SIZE * 4;
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smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
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break;
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case CHIP_CAICOS:
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chip_name = "CAICOS";
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@ -719,6 +725,7 @@ int ni_init_microcode(struct radeon_device *rdev)
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me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
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rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
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mc_req_size = BTC_MC_UCODE_SIZE * 4;
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smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
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break;
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case CHIP_CAYMAN:
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chip_name = "CAYMAN";
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@ -789,6 +796,20 @@ int ni_init_microcode(struct radeon_device *rdev)
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err = -EINVAL;
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}
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}
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if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAICOS)) {
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snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
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err = request_firmware(&rdev->smc_fw, fw_name, &pdev->dev);
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if (err)
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goto out;
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if (rdev->smc_fw->size != smc_req_size) {
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printk(KERN_ERR
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"ni_mc: Bogus length %zu in firmware \"%s\"\n",
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rdev->mc_fw->size, fw_name);
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err = -EINVAL;
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}
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}
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out:
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platform_device_unregister(pdev);
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@ -1722,6 +1722,18 @@ static struct radeon_asic btc_asic = {
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.set_uvd_clocks = &evergreen_set_uvd_clocks,
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.get_temperature = &evergreen_get_temp,
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},
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.dpm = {
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.init = &btc_dpm_init,
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.setup_asic = &btc_dpm_setup_asic,
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.enable = &btc_dpm_enable,
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.disable = &btc_dpm_disable,
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.set_power_state = &btc_dpm_set_power_state,
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.display_configuration_changed = &cypress_dpm_display_configuration_changed,
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.fini = &btc_dpm_fini,
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.get_sclk = &rv770_dpm_get_sclk,
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.get_mclk = &rv770_dpm_get_mclk,
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.print_power_state = &rv770_dpm_print_power_state,
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},
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.pflip = {
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.pre_page_flip = &evergreen_pre_page_flip,
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.page_flip = &evergreen_page_flip,
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@ -536,6 +536,12 @@ void cypress_dpm_disable(struct radeon_device *rdev);
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int cypress_dpm_set_power_state(struct radeon_device *rdev);
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void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
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void cypress_dpm_fini(struct radeon_device *rdev);
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int btc_dpm_init(struct radeon_device *rdev);
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void btc_dpm_setup_asic(struct radeon_device *rdev);
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int btc_dpm_enable(struct radeon_device *rdev);
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void btc_dpm_disable(struct radeon_device *rdev);
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int btc_dpm_set_power_state(struct radeon_device *rdev);
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void btc_dpm_fini(struct radeon_device *rdev);
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/*
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* cayman
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@ -1046,6 +1046,9 @@ int radeon_pm_init(struct radeon_device *rdev)
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case CHIP_JUNIPER:
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case CHIP_CYPRESS:
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case CHIP_HEMLOCK:
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case CHIP_BARTS:
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case CHIP_TURKS:
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case CHIP_CAICOS:
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if (radeon_dpm == 1)
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rdev->pm.pm_method = PM_METHOD_DPM;
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else
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@ -85,4 +85,19 @@
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#define CYPRESS_SMC_INT_VECTOR_START 0xffc0
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#define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040
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#define BARTS_SMC_UCODE_START 0x0100
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#define BARTS_SMC_UCODE_SIZE 0x6107
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#define BARTS_SMC_INT_VECTOR_START 0xffc0
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#define BARTS_SMC_INT_VECTOR_SIZE 0x0040
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#define TURKS_SMC_UCODE_START 0x0100
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#define TURKS_SMC_UCODE_SIZE 0x605b
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#define TURKS_SMC_INT_VECTOR_START 0xffc0
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#define TURKS_SMC_INT_VECTOR_SIZE 0x0040
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#define CAICOS_SMC_UCODE_START 0x0100
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#define CAICOS_SMC_UCODE_SIZE 0x5fbd
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#define CAICOS_SMC_INT_VECTOR_START 0xffc0
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||||
#define CAICOS_SMC_INT_VECTOR_SIZE 0x0040
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -194,6 +194,66 @@ static const u8 cypress_smc_int_vectors[] =
|
|||
0x04, 0xF6, 0x04, 0xF6
|
||||
};
|
||||
|
||||
static const u8 barts_smc_int_vectors[] =
|
||||
{
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x12, 0xAA,
|
||||
0x0C, 0x2F, 0x15, 0xF6,
|
||||
0x15, 0xF6, 0x05, 0x0A,
|
||||
0x05, 0x0A, 0x05, 0x0A
|
||||
};
|
||||
|
||||
static const u8 turks_smc_int_vectors[] =
|
||||
{
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x12, 0xAA,
|
||||
0x0C, 0x2F, 0x15, 0xF6,
|
||||
0x15, 0xF6, 0x05, 0x0A,
|
||||
0x05, 0x0A, 0x05, 0x0A
|
||||
};
|
||||
|
||||
static const u8 caicos_smc_int_vectors[] =
|
||||
{
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x0C, 0x14,
|
||||
0x0C, 0x14, 0x12, 0xAA,
|
||||
0x0C, 0x2F, 0x15, 0xF6,
|
||||
0x15, 0xF6, 0x05, 0x0A,
|
||||
0x05, 0x0A, 0x05, 0x0A
|
||||
};
|
||||
|
||||
int rv770_set_smc_sram_address(struct radeon_device *rdev,
|
||||
u16 smc_address, u16 limit)
|
||||
{
|
||||
|
|
@ -463,6 +523,27 @@ int rv770_load_smc_ucode(struct radeon_device *rdev,
|
|||
int_vect_start_address = CYPRESS_SMC_INT_VECTOR_START;
|
||||
int_vect_size = CYPRESS_SMC_INT_VECTOR_SIZE;
|
||||
break;
|
||||
case CHIP_BARTS:
|
||||
ucode_start_address = BARTS_SMC_UCODE_START;
|
||||
ucode_size = BARTS_SMC_UCODE_SIZE;
|
||||
int_vect = (const u8 *)&barts_smc_int_vectors;
|
||||
int_vect_start_address = BARTS_SMC_INT_VECTOR_START;
|
||||
int_vect_size = BARTS_SMC_INT_VECTOR_SIZE;
|
||||
break;
|
||||
case CHIP_TURKS:
|
||||
ucode_start_address = TURKS_SMC_UCODE_START;
|
||||
ucode_size = TURKS_SMC_UCODE_SIZE;
|
||||
int_vect = (const u8 *)&turks_smc_int_vectors;
|
||||
int_vect_start_address = TURKS_SMC_INT_VECTOR_START;
|
||||
int_vect_size = TURKS_SMC_INT_VECTOR_SIZE;
|
||||
break;
|
||||
case CHIP_CAICOS:
|
||||
ucode_start_address = CAICOS_SMC_UCODE_START;
|
||||
ucode_size = CAICOS_SMC_UCODE_SIZE;
|
||||
int_vect = (const u8 *)&caicos_smc_int_vectors;
|
||||
int_vect_start_address = CAICOS_SMC_INT_VECTOR_START;
|
||||
int_vect_size = CAICOS_SMC_INT_VECTOR_SIZE;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("unknown asic in smc ucode loader\n");
|
||||
BUG();
|
||||
|
|
|
|||
Loading…
Reference in New Issue