From 57eb14779dfd8fa550a5d78f3e971dbf988cd383 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 25 May 2022 16:43:57 +0200 Subject: [PATCH 01/20] interconnect: qcom: icc-rpmh: Support child NoC device probe As per e39bf2972c6e ("interconnect: icc-rpm: Support child NoC device probe") also update the rpmh interconnect driver to support probing NoCs that are modelled as child devices of a different NoC. As the driver doesn't yet use the 'reg' property, no change is done for that. Downstream DT reference: https://android.googlesource.com/kernel/msm-extra/devicetree/+/refs/tags/android-11.0.0_r0.56/qcom/lagoon-bus.dtsi Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20220525144404.200390-2-luca.weiss@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpmh.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 3c40076eb5fb..8acc8e67a332 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -258,6 +258,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) data->num_nodes = num_nodes; platform_set_drvdata(pdev, qp); + /* Populate child NoC devices if any */ + if (of_get_child_count(dev->of_node) > 0) + return of_platform_populate(dev->of_node, NULL, NULL, dev); + return 0; err: icc_nodes_remove(provider); From 23c136bb3f916da4252c79dd4dce07ecbe8ea06e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 25 May 2022 16:43:58 +0200 Subject: [PATCH 02/20] dt-bindings: interconnect: qcom: Split out rpmh-common bindings In preparation for the platforms, split out common definitions used in rpmh-based interconnects. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220525144404.200390-3-luca.weiss@fairphone.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,rpmh-common.yaml | 43 +++++++++++++++++++ .../bindings/interconnect/qcom,rpmh.yaml | 22 +++------- 2 files changed, 48 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml new file mode 100644 index 000000000000..bbeb0541536b --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh-common.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,rpmh-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect + +maintainers: + - Georgi Djakov + - Bjorn Andersson + +description: + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + '#interconnect-cells': + enum: [ 1, 2 ] + + qcom,bcm-voters: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + maxItems: 2 + description: + List of phandles to qcom,bcm-voter nodes that are required by + this interconnect to send RPMh commands. + + qcom,bcm-voter-names: + maxItems: 2 + description: + Names for each of the qcom,bcm-voters specified. + +required: + - '#interconnect-cells' + - qcom,bcm-voters + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 28b3516aa089..a429a1ed1006 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -18,6 +18,9 @@ description: | least one RPMh device child node pertaining to their RSC and each provider can map to multiple RPMh resources. +allOf: + - $ref: qcom,rpmh-common.yaml# + properties: reg: maxItems: 1 @@ -130,28 +133,13 @@ properties: - qcom,sm8450-pcie-anoc - qcom,sm8450-system-noc - '#interconnect-cells': - enum: [ 1, 2 ] - - qcom,bcm-voters: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 - description: | - List of phandles to qcom,bcm-voter nodes that are required by - this interconnect to send RPMh commands. - - qcom,bcm-voter-names: - description: | - Names for each of the qcom,bcm-voters specified. + '#interconnect-cells': true required: - compatible - reg - - '#interconnect-cells' - - qcom,bcm-voters -additionalProperties: false +unevaluatedProperties: false examples: - | From 394fb16954793d387e375b645d44fcfd8602bfda Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 25 May 2022 16:43:59 +0200 Subject: [PATCH 03/20] dt-bindings: interconnect: Add Qualcomm SM6350 NoC support Add bindings for Qualcomm SM6350 Network-On-Chip interconnect devices. As SM6350 has two pairs of NoCs sharing the same reg, allow this in the binding documentation, as was done for qcm2290. Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220525144404.200390-4-luca.weiss@fairphone.com Signed-off-by: Georgi Djakov --- .../interconnect/qcom,sm6350-rpmh.yaml | 82 ++++++++++ .../dt-bindings/interconnect/qcom,sm6350.h | 148 ++++++++++++++++++ 2 files changed, 230 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,sm6350.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml new file mode 100644 index 000000000000..49eb156b08e0 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6350-rpmh.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm6350-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 RPMh Network-On-Chip Interconnect + +maintainers: + - Luca Weiss + +description: + Qualcomm RPMh-based interconnect provider on SM6350. + +allOf: + - $ref: qcom,rpmh-common.yaml# + +properties: + compatible: + enum: + - qcom,sm6350-aggre1-noc + - qcom,sm6350-aggre2-noc + - qcom,sm6350-config-noc + - qcom,sm6350-dc-noc + - qcom,sm6350-gem-noc + - qcom,sm6350-mmss-noc + - qcom,sm6350-npu-noc + - qcom,sm6350-system-noc + + reg: + maxItems: 1 + + '#interconnect-cells': true + +patternProperties: + '^interconnect-[a-z0-9\-]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + $ref: qcom,rpmh-common.yaml# + + properties: + compatible: + enum: + - qcom,sm6350-clk-virt + - qcom,sm6350-compute-noc + + '#interconnect-cells': true + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + config_noc: interconnect@1500000 { + compatible = "qcom,sm6350-config-noc"; + reg = <0x01500000 0x28000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sm6350-system-noc"; + reg = <0x01620000 0x17080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sm6350-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/include/dt-bindings/interconnect/qcom,sm6350.h b/include/dt-bindings/interconnect/qcom,sm6350.h new file mode 100644 index 000000000000..e662cede9aaa --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm6350.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Qualcomm SM6350 interconnect IDs + * + * Copyright (C) 2022 Luca Weiss + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_QUP_0 1 +#define MASTER_EMMC 2 +#define MASTER_UFS_MEM 3 +#define A1NOC_SNOC_SLV 4 +#define SLAVE_SERVICE_A1NOC 5 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_QUP_1 2 +#define MASTER_CRYPTO_CORE_0 3 +#define MASTER_IPA 4 +#define MASTER_QDSS_ETR 5 +#define MASTER_SDCC_2 6 +#define MASTER_USB3 7 +#define A2NOC_SNOC_SLV 8 +#define SLAVE_SERVICE_A2NOC 9 + +#define MASTER_CAMNOC_HF0_UNCOMP 0 +#define MASTER_CAMNOC_ICP_UNCOMP 1 +#define MASTER_CAMNOC_SF_UNCOMP 2 +#define MASTER_QUP_CORE_0 3 +#define MASTER_QUP_CORE_1 4 +#define MASTER_LLCC 5 +#define SLAVE_CAMNOC_UNCOMP 6 +#define SLAVE_QUP_CORE_0 7 +#define SLAVE_QUP_CORE_1 8 +#define SLAVE_EBI_CH0 9 + +#define MASTER_NPU 0 +#define MASTER_NPU_PROC 1 +#define SLAVE_CDSP_GEM_NOC 2 + +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AHB2PHY 4 +#define SLAVE_AHB2PHY_2 5 +#define SLAVE_AOSS 6 +#define SLAVE_BOOT_ROM 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 9 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_RBCPR_CX_CFG 12 +#define SLAVE_RBCPR_MX_CFG 13 +#define SLAVE_CRYPTO_0_CFG 14 +#define SLAVE_DCC_CFG 15 +#define SLAVE_CNOC_DDRSS 16 +#define SLAVE_DISPLAY_CFG 17 +#define SLAVE_DISPLAY_THROTTLE_CFG 18 +#define SLAVE_EMMC_CFG 19 +#define SLAVE_GLM 20 +#define SLAVE_GRAPHICS_3D_CFG 21 +#define SLAVE_IMEM_CFG 22 +#define SLAVE_IPA_CFG 23 +#define SLAVE_CNOC_MNOC_CFG 24 +#define SLAVE_CNOC_MSS 25 +#define SLAVE_NPU_CFG 26 +#define SLAVE_PDM 27 +#define SLAVE_PIMEM_CFG 28 +#define SLAVE_PRNG 29 +#define SLAVE_QDSS_CFG 30 +#define SLAVE_QM_CFG 31 +#define SLAVE_QM_MPU_CFG 32 +#define SLAVE_QUP_0 33 +#define SLAVE_QUP_1 34 +#define SLAVE_SDCC_2 35 +#define SLAVE_SECURITY 36 +#define SLAVE_SNOC_CFG 37 +#define SLAVE_TCSR 38 +#define SLAVE_UFS_MEM_CFG 39 +#define SLAVE_USB3 40 +#define SLAVE_VENUS_CFG 41 +#define SLAVE_VENUS_THROTTLE_CFG 42 +#define SLAVE_VSENSE_CTRL_CFG 43 +#define SLAVE_SERVICE_CNOC 44 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_GEM_NOC_CFG 1 +#define SLAVE_LLCC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_SYS_TCU 1 +#define MASTER_GEM_NOC_CFG 2 +#define MASTER_COMPUTE_NOC 3 +#define MASTER_MNOC_HF_MEM_NOC 4 +#define MASTER_MNOC_SF_MEM_NOC 5 +#define MASTER_SNOC_GC_MEM_NOC 6 +#define MASTER_SNOC_SF_MEM_NOC 7 +#define MASTER_GRAPHICS_3D 8 +#define SLAVE_MCDMA_MS_MPU_CFG 9 +#define SLAVE_MSS_PROC_MS_MPU_CFG 10 +#define SLAVE_GEM_NOC_SNOC 11 +#define SLAVE_LLCC 12 +#define SLAVE_SERVICE_GEM_NOC 13 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define MASTER_CAMNOC_HF 3 +#define MASTER_CAMNOC_ICP 4 +#define MASTER_CAMNOC_SF 5 +#define MASTER_MDP_PORT0 6 +#define SLAVE_MNOC_HF_MEM_NOC 7 +#define SLAVE_MNOC_SF_MEM_NOC 8 +#define SLAVE_SERVICE_MNOC 9 + +#define MASTER_NPU_SYS 0 +#define MASTER_NPU_NOC_CFG 1 +#define SLAVE_NPU_CAL_DP0 2 +#define SLAVE_NPU_CP 3 +#define SLAVE_NPU_INT_DMA_BWMON_CFG 4 +#define SLAVE_NPU_DPM 5 +#define SLAVE_ISENSE_CFG 6 +#define SLAVE_NPU_LLM_CFG 7 +#define SLAVE_NPU_TCM 8 +#define SLAVE_NPU_COMPUTE_NOC 9 +#define SLAVE_SERVICE_NPU_NOC 10 + +#define MASTER_SNOC_CFG 0 +#define A1NOC_SNOC_MAS 1 +#define A2NOC_SNOC_MAS 2 +#define MASTER_GEM_NOC_SNOC 3 +#define MASTER_PIMEM 4 +#define MASTER_GIC 5 +#define SLAVE_APPSS 6 +#define SNOC_CNOC_SLV 7 +#define SLAVE_SNOC_GEM_NOC_GC 8 +#define SLAVE_SNOC_GEM_NOC_SF 9 +#define SLAVE_OCIMEM 10 +#define SLAVE_PIMEM 11 +#define SLAVE_SERVICE_SNOC 12 +#define SLAVE_QDSS_STM 13 +#define SLAVE_TCU 14 + +#endif From 6a6eff73a9542141624ad4b27ddbc13f9f3f7103 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 25 May 2022 16:44:00 +0200 Subject: [PATCH 04/20] interconnect: qcom: Add SM6350 driver support Add a driver that handles the different NoCs found on SM6350, generated from the downstream dtb. We're exluding ALC, IP0 and all _display nodes. ALC will not be voted from the kernel[1] and IP0 is handled by the clk-rpmh driver[2]. [1] https://lore.kernel.org/linux-arm-msm/1e79c73f22c8891dc9f868babd940fca@codeaurora.org/ [2] https://lore.kernel.org/linux-arm-msm/20220412220033.1273607-1-swboyd@chromium.org/ Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20220525144404.200390-5-luca.weiss@fairphone.com Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sm6350.c | 493 +++++++++++++++++++++++++++++ drivers/interconnect/qcom/sm6350.h | 139 ++++++++ 4 files changed, 643 insertions(+) create mode 100644 drivers/interconnect/qcom/sm6350.c create mode 100644 drivers/interconnect/qcom/sm6350.h diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index 22adff5d7f53..25d5b4baf6f6 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -155,6 +155,15 @@ config INTERCONNECT_QCOM_SDX65 This is a driver for the Qualcomm Network-on-Chip on sdx65-based platforms. +config INTERCONNECT_QCOM_SM6350 + tristate "Qualcomm SM6350 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sm6350-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 8d1fe9d38ac3..120e279a7427 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -17,6 +17,7 @@ qnoc-sdm660-objs := sdm660.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o +qnoc-sm6350-objs := sm6350.o qnoc-sm8150-objs := sm8150.o qnoc-sm8250-objs := sm8250.o qnoc-sm8350-objs := sm8350.o @@ -40,6 +41,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c new file mode 100644 index 000000000000..a3d46e59444e --- /dev/null +++ b/drivers/interconnect/qcom/sm6350.c @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Luca Weiss + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sm6350.h" + +DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC); +DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV); +DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC); +DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); +DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0); +DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1); +DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); +DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC); +DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); +DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); +DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); +DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG); +DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC); +DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC); +DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); +DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); +DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC); +DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC); +DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); +DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC); +DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); +DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM); +DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC); +DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS); +DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); +DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS); +DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); +DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); +DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); +DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); +DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC); +DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG); +DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG); +DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); +DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); +DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); +DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); +DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); +DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); +DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); +DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); +DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); +DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); +DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC); +DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); +DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); +DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); +DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); +DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); +DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); +DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG); +DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); +DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); +DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); +DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); +DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); +DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); +DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); +DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); +DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); +DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG); +DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); +DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); +DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); +DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); +DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4); +DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); +DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); +DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG); +DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); +DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); +DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); +DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC); +DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); +DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); +DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); +DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC); +DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); +DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); +DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); +DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); +DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); +DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); +DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); +DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); +DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); +DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); +DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); +DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); +DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC); +DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC); +DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); +DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); +DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); +DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); +DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); + +DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); +DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); +DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); +DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2); +DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); +DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); +DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); +DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); +DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); +DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); +DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); +DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave); +DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); +DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); +DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); +DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); +DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); +DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); +DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); +DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); +DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); +DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); +DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); +DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_cn1, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, + [MASTER_QUP_0] = &qhm_qup_0, + [MASTER_EMMC] = &xm_emmc, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, +}; + +static const struct qcom_icc_desc sm6350_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_1] = &qhm_qup_1, + [MASTER_CRYPTO_CORE_0] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_USB3] = &xm_usb3_0, + [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static const struct qcom_icc_desc sm6350_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, + &bcm_mm1, + &bcm_qup0, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] = { + [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, + [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp, + [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_LLCC] = &llcc_mc, + [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_EBI_CH0] = &ebi, +}; + +static const struct qcom_icc_desc sm6350_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const compute_noc_bcms[] = { + &bcm_co0, + &bcm_co2, + &bcm_co3, +}; + +static struct qcom_icc_node * const compute_noc_nodes[] = { + [MASTER_NPU] = &qnm_npu, + [MASTER_NPU_PROC] = &qxm_npu_dsp, + [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, +}; + +static const struct qcom_icc_desc sm6350_compute_noc = { + .nodes = compute_noc_nodes, + .num_nodes = ARRAY_SIZE(compute_noc_nodes), + .bcms = compute_noc_bcms, + .num_bcms = ARRAY_SIZE(compute_noc_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [SNOC_CNOC_MAS] = &qnm_snoc, + [MASTER_QDSS_DAP] = &xm_qdss_dap, + [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, + [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, + [SLAVE_AHB2PHY] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_BOOT_ROM] = &qhs_boot_rom, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DCC_CFG] = &qhs_dcc_cfg, + [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, + [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, + [SLAVE_GLM] = &qhs_glm, + [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, + [SLAVE_CNOC_MSS] = &qhs_mss_cfg, + [SLAVE_NPU_CFG] = &qhs_npu_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QM_CFG] = &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static const struct qcom_icc_desc sm6350_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const dc_noc_bcms[] = { +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, + [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, + [SLAVE_LLCC_CFG] = &qhs_llcc, +}; + +static const struct qcom_icc_desc sm6350_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms = ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, + &bcm_sh3, + &bcm_sh4, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] = { + [MASTER_AMPSS_M0] = &acm_apps, + [MASTER_SYS_TCU] = &acm_sys_tcu, + [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_GRAPHICS_3D] = &qxm_gpu, + [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg, + [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, + [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, +}; + +static const struct qcom_icc_desc sm6350_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm2, + &bcm_mm3, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, + [MASTER_VIDEO_P0] = &qnm_video0, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, + [MASTER_MDP_PORT0] = &qxm_mdp0, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sm6350_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const npu_noc_bcms[] = { +}; + +static struct qcom_icc_node * const npu_noc_nodes[] = { + [MASTER_NPU_SYS] = &amm_npu_sys, + [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, + [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, + [SLAVE_NPU_CP] = &qhs_cp, + [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, + [SLAVE_NPU_DPM] = &qhs_dpm, + [SLAVE_ISENSE_CFG] = &qhs_isense, + [SLAVE_NPU_LLM_CFG] = &qhs_llm, + [SLAVE_NPU_TCM] = &qhs_tcm, + [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, + [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, +}; + +static const struct qcom_icc_desc sm6350_npu_noc = { + .nodes = npu_noc_nodes, + .num_nodes = ARRAY_SIZE(npu_noc_nodes), + .bcms = npu_noc_bcms, + .num_bcms = ARRAY_SIZE(npu_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn10, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, + &bcm_sn5, + &bcm_sn6, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, + [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, + [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_APPSS] = &qhs_apss, + [SNOC_CNOC_SLV] = &qns_cnoc, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_OCIMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sm6350_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sm6350-aggre1-noc", + .data = &sm6350_aggre1_noc}, + { .compatible = "qcom,sm6350-aggre2-noc", + .data = &sm6350_aggre2_noc}, + { .compatible = "qcom,sm6350-clk-virt", + .data = &sm6350_clk_virt}, + { .compatible = "qcom,sm6350-compute-noc", + .data = &sm6350_compute_noc}, + { .compatible = "qcom,sm6350-config-noc", + .data = &sm6350_config_noc}, + { .compatible = "qcom,sm6350-dc-noc", + .data = &sm6350_dc_noc}, + { .compatible = "qcom,sm6350-gem-noc", + .data = &sm6350_gem_noc}, + { .compatible = "qcom,sm6350-mmss-noc", + .data = &sm6350_mmss_noc}, + { .compatible = "qcom,sm6350-npu-noc", + .data = &sm6350_npu_noc}, + { .compatible = "qcom,sm6350-system-noc", + .data = &sm6350_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sm6350", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; +module_platform_driver(qnoc_driver); + +MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/sm6350.h b/drivers/interconnect/qcom/sm6350.h new file mode 100644 index 000000000000..43cf2930c88a --- /dev/null +++ b/drivers/interconnect/qcom/sm6350.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm #define SM6350 interconnect IDs + * + * Copyright (C) 2022 Luca Weiss + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SM6350_H +#define __DRIVERS_INTERCONNECT_QCOM_SM6350_H + +#define SM6350_A1NOC_SNOC_MAS 0 +#define SM6350_A1NOC_SNOC_SLV 1 +#define SM6350_A2NOC_SNOC_MAS 2 +#define SM6350_A2NOC_SNOC_SLV 3 +#define SM6350_MASTER_A1NOC_CFG 4 +#define SM6350_MASTER_A2NOC_CFG 5 +#define SM6350_MASTER_AMPSS_M0 6 +#define SM6350_MASTER_CAMNOC_HF 7 +#define SM6350_MASTER_CAMNOC_HF0_UNCOMP 8 +#define SM6350_MASTER_CAMNOC_ICP 9 +#define SM6350_MASTER_CAMNOC_ICP_UNCOMP 10 +#define SM6350_MASTER_CAMNOC_SF 11 +#define SM6350_MASTER_CAMNOC_SF_UNCOMP 12 +#define SM6350_MASTER_CNOC_DC_NOC 13 +#define SM6350_MASTER_CNOC_MNOC_CFG 14 +#define SM6350_MASTER_COMPUTE_NOC 15 +#define SM6350_MASTER_CRYPTO_CORE_0 16 +#define SM6350_MASTER_EMMC 17 +#define SM6350_MASTER_GEM_NOC_CFG 18 +#define SM6350_MASTER_GEM_NOC_SNOC 19 +#define SM6350_MASTER_GIC 20 +#define SM6350_MASTER_GRAPHICS_3D 21 +#define SM6350_MASTER_IPA 22 +#define SM6350_MASTER_LLCC 23 +#define SM6350_MASTER_MDP_PORT0 24 +#define SM6350_MASTER_MNOC_HF_MEM_NOC 25 +#define SM6350_MASTER_MNOC_SF_MEM_NOC 26 +#define SM6350_MASTER_NPU 27 +#define SM6350_MASTER_NPU_NOC_CFG 28 +#define SM6350_MASTER_NPU_PROC 29 +#define SM6350_MASTER_NPU_SYS 30 +#define SM6350_MASTER_PIMEM 31 +#define SM6350_MASTER_QDSS_BAM 32 +#define SM6350_MASTER_QDSS_DAP 33 +#define SM6350_MASTER_QDSS_ETR 34 +#define SM6350_MASTER_QUP_0 35 +#define SM6350_MASTER_QUP_1 36 +#define SM6350_MASTER_QUP_CORE_0 37 +#define SM6350_MASTER_QUP_CORE_1 38 +#define SM6350_MASTER_SDCC_2 39 +#define SM6350_MASTER_SNOC_CFG 40 +#define SM6350_MASTER_SNOC_GC_MEM_NOC 41 +#define SM6350_MASTER_SNOC_SF_MEM_NOC 42 +#define SM6350_MASTER_SYS_TCU 43 +#define SM6350_MASTER_UFS_MEM 44 +#define SM6350_MASTER_USB3 45 +#define SM6350_MASTER_VIDEO_P0 46 +#define SM6350_MASTER_VIDEO_PROC 47 +#define SM6350_SLAVE_A1NOC_CFG 48 +#define SM6350_SLAVE_A2NOC_CFG 49 +#define SM6350_SLAVE_AHB2PHY 50 +#define SM6350_SLAVE_AHB2PHY_2 51 +#define SM6350_SLAVE_AOSS 52 +#define SM6350_SLAVE_APPSS 53 +#define SM6350_SLAVE_BOOT_ROM 54 +#define SM6350_SLAVE_CAMERA_CFG 55 +#define SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG 56 +#define SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG 57 +#define SM6350_SLAVE_CAMNOC_UNCOMP 58 +#define SM6350_SLAVE_CDSP_GEM_NOC 59 +#define SM6350_SLAVE_CLK_CTL 60 +#define SM6350_SLAVE_CNOC_DDRSS 61 +#define SM6350_SLAVE_CNOC_MNOC_CFG 62 +#define SM6350_SLAVE_CNOC_MSS 63 +#define SM6350_SLAVE_CRYPTO_0_CFG 64 +#define SM6350_SLAVE_DCC_CFG 65 +#define SM6350_SLAVE_DISPLAY_CFG 66 +#define SM6350_SLAVE_DISPLAY_THROTTLE_CFG 67 +#define SM6350_SLAVE_EBI_CH0 68 +#define SM6350_SLAVE_EMMC_CFG 69 +#define SM6350_SLAVE_GEM_NOC_CFG 70 +#define SM6350_SLAVE_GEM_NOC_SNOC 71 +#define SM6350_SLAVE_GLM 72 +#define SM6350_SLAVE_GRAPHICS_3D_CFG 73 +#define SM6350_SLAVE_IMEM_CFG 74 +#define SM6350_SLAVE_IPA_CFG 75 +#define SM6350_SLAVE_ISENSE_CFG 76 +#define SM6350_SLAVE_LLCC 77 +#define SM6350_SLAVE_LLCC_CFG 78 +#define SM6350_SLAVE_MCDMA_MS_MPU_CFG 79 +#define SM6350_SLAVE_MNOC_HF_MEM_NOC 80 +#define SM6350_SLAVE_MNOC_SF_MEM_NOC 81 +#define SM6350_SLAVE_MSS_PROC_MS_MPU_CFG 82 +#define SM6350_SLAVE_NPU_CAL_DP0 83 +#define SM6350_SLAVE_NPU_CFG 84 +#define SM6350_SLAVE_NPU_COMPUTE_NOC 85 +#define SM6350_SLAVE_NPU_CP 86 +#define SM6350_SLAVE_NPU_DPM 87 +#define SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG 88 +#define SM6350_SLAVE_NPU_LLM_CFG 89 +#define SM6350_SLAVE_NPU_TCM 90 +#define SM6350_SLAVE_OCIMEM 91 +#define SM6350_SLAVE_PDM 92 +#define SM6350_SLAVE_PIMEM 93 +#define SM6350_SLAVE_PIMEM_CFG 94 +#define SM6350_SLAVE_PRNG 95 +#define SM6350_SLAVE_QDSS_CFG 96 +#define SM6350_SLAVE_QDSS_STM 97 +#define SM6350_SLAVE_QM_CFG 98 +#define SM6350_SLAVE_QM_MPU_CFG 99 +#define SM6350_SLAVE_QUP_0 100 +#define SM6350_SLAVE_QUP_1 101 +#define SM6350_SLAVE_QUP_CORE_0 102 +#define SM6350_SLAVE_QUP_CORE_1 103 +#define SM6350_SLAVE_RBCPR_CX_CFG 104 +#define SM6350_SLAVE_RBCPR_MX_CFG 105 +#define SM6350_SLAVE_SDCC_2 106 +#define SM6350_SLAVE_SECURITY 107 +#define SM6350_SLAVE_SERVICE_A1NOC 108 +#define SM6350_SLAVE_SERVICE_A2NOC 109 +#define SM6350_SLAVE_SERVICE_CNOC 110 +#define SM6350_SLAVE_SERVICE_GEM_NOC 111 +#define SM6350_SLAVE_SERVICE_MNOC 112 +#define SM6350_SLAVE_SERVICE_NPU_NOC 113 +#define SM6350_SLAVE_SERVICE_SNOC 114 +#define SM6350_SLAVE_SNOC_CFG 115 +#define SM6350_SLAVE_SNOC_GEM_NOC_GC 116 +#define SM6350_SLAVE_SNOC_GEM_NOC_SF 117 +#define SM6350_SLAVE_TCSR 118 +#define SM6350_SLAVE_TCU 119 +#define SM6350_SLAVE_UFS_MEM_CFG 120 +#define SM6350_SLAVE_USB3 121 +#define SM6350_SLAVE_VENUS_CFG 122 +#define SM6350_SLAVE_VENUS_THROTTLE_CFG 123 +#define SM6350_SLAVE_VSENSE_CTRL_CFG 124 +#define SM6350_SNOC_CNOC_MAS 125 +#define SM6350_SNOC_CNOC_SLV 126 + +#endif From 740115505ed4f4e7597c75ed6dd9af4d610ddb85 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:23 +0800 Subject: [PATCH 05/20] dt-bindings: interconnect: imx8m: Add bindings for imx8mp noc i.MX8MP features same NoC/NIC as i.MX8MM/N/Q, and use two compatible strings. Signed-off-by: Peng Fan Acked-by: Rob Herring Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220703091132.1412063-2-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/fsl,imx8m-noc.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml index b8204ed22dd5..09c8948b5e25 100644 --- a/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml +++ b/Documentation/devicetree/bindings/interconnect/fsl,imx8m-noc.yaml @@ -26,14 +26,16 @@ properties: oneOf: - items: - enum: - - fsl,imx8mn-nic - fsl,imx8mm-nic + - fsl,imx8mn-nic + - fsl,imx8mp-nic - fsl,imx8mq-nic - const: fsl,imx8m-nic - items: - enum: - - fsl,imx8mn-noc - fsl,imx8mm-noc + - fsl,imx8mn-noc + - fsl,imx8mp-noc - fsl,imx8mq-noc - const: fsl,imx8m-noc - const: fsl,imx8m-nic From e2a4a0eeb0cd308bb96d168f90c225da2084d4dc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:24 +0800 Subject: [PATCH 06/20] dt-bindings: interconnect: add fsl,imx8mp.h Add fsl,imx8mp.h for i.MX8MP Signed-off-by: Peng Fan Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220703091132.1412063-3-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- include/dt-bindings/interconnect/fsl,imx8mp.h | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/interconnect/fsl,imx8mp.h diff --git a/include/dt-bindings/interconnect/fsl,imx8mp.h b/include/dt-bindings/interconnect/fsl,imx8mp.h new file mode 100644 index 000000000000..7357d417529a --- /dev/null +++ b/include/dt-bindings/interconnect/fsl,imx8mp.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright 2022 NXP + * Peng Fan + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H + +#define IMX8MP_ICN_NOC 0 +#define IMX8MP_ICN_MAIN 1 +#define IMX8MP_ICS_DRAM 2 +#define IMX8MP_ICS_OCRAM 3 +#define IMX8MP_ICM_A53 4 +#define IMX8MP_ICM_SUPERMIX 5 +#define IMX8MP_ICM_GIC 6 +#define IMX8MP_ICM_MLMIX 7 + +#define IMX8MP_ICN_AUDIO 8 +#define IMX8MP_ICM_DSP 9 +#define IMX8MP_ICM_SDMA2PER 10 +#define IMX8MP_ICM_SDMA2BURST 11 +#define IMX8MP_ICM_SDMA3PER 12 +#define IMX8MP_ICM_SDMA3BURST 13 +#define IMX8MP_ICM_EDMA 14 + +#define IMX8MP_ICN_GPU 15 +#define IMX8MP_ICM_GPU2D 16 +#define IMX8MP_ICM_GPU3D 17 + +#define IMX8MP_ICN_HDMI 18 +#define IMX8MP_ICM_HRV 19 +#define IMX8MP_ICM_LCDIF_HDMI 20 +#define IMX8MP_ICM_HDCP 21 + +#define IMX8MP_ICN_HSIO 22 +#define IMX8MP_ICM_NOC_PCIE 23 +#define IMX8MP_ICM_USB1 24 +#define IMX8MP_ICM_USB2 25 +#define IMX8MP_ICM_PCIE 26 + +#define IMX8MP_ICN_MEDIA 27 +#define IMX8MP_ICM_LCDIF_RD 28 +#define IMX8MP_ICM_LCDIF_WR 29 +#define IMX8MP_ICM_ISI0 30 +#define IMX8MP_ICM_ISI1 31 +#define IMX8MP_ICM_ISI2 32 +#define IMX8MP_ICM_ISP0 33 +#define IMX8MP_ICM_ISP1 34 +#define IMX8MP_ICM_DWE 35 + +#define IMX8MP_ICN_VIDEO 36 +#define IMX8MP_ICM_VPU_G1 37 +#define IMX8MP_ICM_VPU_G2 38 +#define IMX8MP_ICM_VPU_H1 39 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */ From 2fcfa72fc13f0203bb676bd1ec30ec85e17855be Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:25 +0800 Subject: [PATCH 07/20] interconnect: add device managed bulk API Add device managed bulk API to simplify driver. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-4-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/bulk.c | 42 ++++++++++++++++++++++++++++++++++++ include/linux/interconnect.h | 7 ++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/interconnect/bulk.c b/drivers/interconnect/bulk.c index 448cc536aa79..8b1d8a412464 100644 --- a/drivers/interconnect/bulk.c +++ b/drivers/interconnect/bulk.c @@ -115,3 +115,45 @@ void icc_bulk_disable(int num_paths, const struct icc_bulk_data *paths) icc_disable(paths[num_paths].path); } EXPORT_SYMBOL_GPL(icc_bulk_disable); + +struct icc_bulk_devres { + struct icc_bulk_data *paths; + int num_paths; +}; + +static void devm_icc_bulk_release(struct device *dev, void *res) +{ + struct icc_bulk_devres *devres = res; + + icc_bulk_put(devres->num_paths, devres->paths); +} + +/** + * devm_of_icc_bulk_get() - resource managed of_icc_bulk_get + * @dev: the device requesting the path + * @num_paths: the number of icc_bulk_data + * @paths: the table with the paths we want to get + * + * Returns 0 on success or negative errno otherwise. + */ +int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths) +{ + struct icc_bulk_devres *devres; + int ret; + + devres = devres_alloc(devm_icc_bulk_release, sizeof(*devres), GFP_KERNEL); + if (!devres) + return -ENOMEM; + + ret = of_icc_bulk_get(dev, num_paths, paths); + if (!ret) { + devres->paths = paths; + devres->num_paths = num_paths; + devres_add(dev, devres); + } else { + devres_free(devres); + } + + return ret; +} +EXPORT_SYMBOL_GPL(devm_of_icc_bulk_get); diff --git a/include/linux/interconnect.h b/include/linux/interconnect.h index f685777b875e..2b0e784ba771 100644 --- a/include/linux/interconnect.h +++ b/include/linux/interconnect.h @@ -44,6 +44,7 @@ struct icc_path *icc_get(struct device *dev, const int src_id, const int dst_id); struct icc_path *of_icc_get(struct device *dev, const char *name); struct icc_path *devm_of_icc_get(struct device *dev, const char *name); +int devm_of_icc_bulk_get(struct device *dev, int num_paths, struct icc_bulk_data *paths); struct icc_path *of_icc_get_by_index(struct device *dev, int idx); void icc_put(struct icc_path *path); int icc_enable(struct icc_path *path); @@ -116,6 +117,12 @@ static inline int of_icc_bulk_get(struct device *dev, int num_paths, struct icc_ return 0; } +static inline int devm_of_icc_bulk_get(struct device *dev, int num_paths, + struct icc_bulk_data *paths) +{ + return 0; +} + static inline void icc_bulk_put(int num_paths, struct icc_bulk_data *paths) { } From 76a748e2c1aa976d0c7fef872fa6ff93ce334a8a Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Sat, 16 Apr 2022 09:26:34 +0800 Subject: [PATCH 08/20] interconnect: qcom: msm8939: Use icc_sync_state It's fashion to use the icc_sync_state callback to notify the framework when all consumers are probed, so that the bandwidth request doesn't need to stay on maximum value. Do the same thing for msm8939 driver. Signed-off-by: Leo Yan Link: https://lore.kernel.org/r/20220416012634.479617-1-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/msm8939.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 63b31deea722..caf0aefad668 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -1423,6 +1423,7 @@ static struct platform_driver msm8939_noc_driver = { .driver = { .name = "qnoc-msm8939", .of_match_table = msm8939_noc_of_match, + .sync_state = icc_sync_state, }, }; module_platform_driver(msm8939_noc_driver); From 751f4d14cdb47df3721d1a7431cc1d5a790f9302 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 7 Jul 2022 10:38:23 +0100 Subject: [PATCH 09/20] interconnect: icc-rpm: Set destination bandwidth as well as source bandwidth Make it possible to set destination as well as source bandwidth. If the *dst pointer is non-NULL. Right now it appears that we never make the destination bw allocation call, which is inconsistent with the downstream way of doing this. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20220707093823.1691870-1-bryan.odonoghue@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 41 +++++++++++++++++++++-------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index fb013191c29b..7e8bcbb2f5db 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -233,10 +233,30 @@ static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) return ret; } +static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn, + u64 sum_bw) +{ + int ret; + + if (!qn->qos.ap_owned) { + /* send bandwidth request message to the RPM processor */ + ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); + if (ret) + return ret; + } else if (qn->qos.qos_mode != -1) { + /* set bandwidth directly from the AP */ + ret = qcom_icc_qos_set(n, sum_bw); + if (ret) + return ret; + } + + return 0; +} + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; + struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL; struct icc_provider *provider; struct icc_node *n; u64 sum_bw; @@ -246,7 +266,9 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) u32 agg_peak = 0; int ret, i; - qn = src->data; + src_qn = src->data; + if (dst) + dst_qn = dst->data; provider = src->provider; qp = to_qcom_provider(provider); @@ -257,21 +279,18 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) sum_bw = icc_units_to_bps(agg_avg); max_peak_bw = icc_units_to_bps(agg_peak); - if (!qn->qos.ap_owned) { - /* send bandwidth request message to the RPM processor */ - ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); - if (ret) - return ret; - } else if (qn->qos.qos_mode != -1) { - /* set bandwidth directly from the AP */ - ret = qcom_icc_qos_set(src, sum_bw); + ret = __qcom_icc_set(src, src_qn, sum_bw); + if (ret) + return ret; + if (dst_qn) { + ret = __qcom_icc_set(dst, dst_qn, sum_bw); if (ret) return ret; } rate = max(sum_bw, max_peak_bw); - do_div(rate, qn->buswidth); + do_div(rate, src_qn->buswidth); rate = min_t(u64, rate, LONG_MAX); for (i = 0; i < qp->num_clks; i++) { From 2c510f5bee760a83b1ce0790dcccb8301dd41ce8 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 12 Jul 2022 09:59:25 +0800 Subject: [PATCH 10/20] dt-bindings: interconnect: Update property for icc-rpm path tag To support path tag in icc-rpm driver, the "#interconnect-cells" property is updated as enumerate values: 1 or 2. Setting to 1 means it is compatible with old DT binding that interconnect path only contains node id; if set to 2 for "#interconnect-cells" property, then the second specifier is used as a tag (e.g. vote for which buckets). Signed-off-by: Leo Yan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220712015929.2789881-2-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- .../devicetree/bindings/interconnect/qcom,rpm.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 8a676fef8c1d..4b37aa88a375 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -45,7 +45,11 @@ properties: - qcom,sdm660-snoc '#interconnect-cells': - const: 1 + description: | + Value: <1> is one cell in an interconnect specifier for the + interconnect node id, <2> requires the interconnect node id and an + extra path tag. + enum: [ 1, 2 ] clocks: minItems: 2 From cb4805b5a5e44063d2b194d97e705888eaf59005 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 12 Jul 2022 09:59:26 +0800 Subject: [PATCH 11/20] interconnect: qcom: Move qcom_icc_xlate_extended() to a common file since there have conflict between two headers icc-rpmh.h and icc-rpm.h, the function qcom_icc_xlate_extended() is declared in icc-rpmh.h thus it cannot be used by icc-rpm driver. Move the function to a new common file icc-common.c so that allow it to be called by multiple drivers. Signed-off-by: Leo Yan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220712015929.2789881-3-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/Makefile | 3 +++ drivers/interconnect/qcom/icc-common.c | 34 ++++++++++++++++++++++++++ drivers/interconnect/qcom/icc-common.h | 13 ++++++++++ drivers/interconnect/qcom/icc-rpmh.c | 26 +------------------- drivers/interconnect/qcom/icc-rpmh.h | 1 - drivers/interconnect/qcom/sm8450.c | 1 + 6 files changed, 52 insertions(+), 26 deletions(-) create mode 100644 drivers/interconnect/qcom/icc-common.c create mode 100644 drivers/interconnect/qcom/icc-common.h diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 8d1fe9d38ac3..e6451470f812 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_INTERCONNECT_QCOM) += interconnect_qcom.o + +interconnect_qcom-y := icc-common.o icc-bcm-voter-objs := bcm-voter.o qnoc-msm8916-objs := msm8916.o qnoc-msm8939-objs := msm8939.o diff --git a/drivers/interconnect/qcom/icc-common.c b/drivers/interconnect/qcom/icc-common.c new file mode 100644 index 000000000000..0822ce207b5d --- /dev/null +++ b/drivers/interconnect/qcom/icc-common.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Linaro Ltd. + */ + +#include +#include + +#include "icc-common.h" + +struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_node_data *ndata; + struct icc_node *node; + + node = of_icc_xlate_onecell(spec, data); + if (IS_ERR(node)) + return ERR_CAST(node); + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + ndata->node = node; + + if (spec->args_count == 2) + ndata->tag = spec->args[1]; + + if (spec->args_count > 2) + pr_warn("%pOF: Too many arguments, path tag is not parsed\n", spec->np); + + return ndata; +} +EXPORT_SYMBOL_GPL(qcom_icc_xlate_extended); diff --git a/drivers/interconnect/qcom/icc-common.h b/drivers/interconnect/qcom/icc-common.h new file mode 100644 index 000000000000..33bb2c38dff3 --- /dev/null +++ b/drivers/interconnect/qcom/icc-common.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Linaro Ltd. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_COMMON_H__ +#define __DRIVERS_INTERCONNECT_QCOM_ICC_COMMON_H__ + +#include + +struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data); + +#endif diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index 3c40076eb5fb..505d53e80d96 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -11,6 +11,7 @@ #include #include "bcm-voter.h" +#include "icc-common.h" #include "icc-rpmh.h" /** @@ -100,31 +101,6 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst) } EXPORT_SYMBOL_GPL(qcom_icc_set); -struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data) -{ - struct icc_node_data *ndata; - struct icc_node *node; - - node = of_icc_xlate_onecell(spec, data); - if (IS_ERR(node)) - return ERR_CAST(node); - - ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); - if (!ndata) - return ERR_PTR(-ENOMEM); - - ndata->node = node; - - if (spec->args_count == 2) - ndata->tag = spec->args[1]; - - if (spec->args_count > 2) - pr_warn("%pOF: Too many arguments, path tag is not parsed\n", spec->np); - - return ndata; -} -EXPORT_SYMBOL_GPL(qcom_icc_xlate_extended); - /** * qcom_icc_bcm_init - populates bcm aux data and connect qnodes * @bcm: bcm to be initialized diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index d29929461c17..04391c1ba465 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -131,7 +131,6 @@ struct qcom_icc_desc { int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); int qcom_icc_set(struct icc_node *src, struct icc_node *dst); -struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data); int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev); void qcom_icc_pre_aggregate(struct icc_node *node); int qcom_icc_rpmh_probe(struct platform_device *pdev); diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index 7e3d372b712f..e821fd0b2f66 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -12,6 +12,7 @@ #include #include "bcm-voter.h" +#include "icc-common.h" #include "icc-rpmh.h" #include "sm8450.h" From ad510e4ed2a3b6f195c2aed6fe21a311440b489b Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 12 Jul 2022 09:59:27 +0800 Subject: [PATCH 12/20] interconnect: qcom: icc-rpm: Change to use qcom_icc_xlate_extended() This commit changes to use callback qcom_icc_xlate_extended(). This is a preparation for population path tags from the interconnect DT binding, it doesn't introduce functionality change for the existed DT binding without path tags. Signed-off-by: Leo Yan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220712015929.2789881-4-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 7e8bcbb2f5db..8c9d5cc7276c 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -16,6 +16,7 @@ #include #include "smd-rpm.h" +#include "icc-common.h" #include "icc-rpm.h" /* QNOC QoS */ @@ -414,7 +415,7 @@ int qnoc_probe(struct platform_device *pdev) provider->dev = dev; provider->set = qcom_icc_set; provider->aggregate = icc_std_aggregate; - provider->xlate = of_icc_xlate_onecell; + provider->xlate_extended = qcom_icc_xlate_extended; provider->data = data; ret = icc_provider_add(provider); From dcbce7b0a79cc5bc16759079090e1a3aa8dfea34 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 12 Jul 2022 09:59:28 +0800 Subject: [PATCH 13/20] interconnect: qcom: icc-rpm: Support multiple buckets The current interconnect rpm driver uses a single aggregate bandwidth to calculate the clock rates for both active and sleep clocks; therefore, it has no chance to separate bandwidth requests for these two kinds of clocks. This patch studies the implementation from interconnect rpmh driver to support multiple buckets. The rpmh driver provides three buckets for AMC, WAKE, and SLEEP; this driver only needs to use WAKE and SLEEP buckets, but we keep the same way with rpmh driver, this can allow us to reuse the DT binding and avoid to define duplicated data structures. This patch introduces two callbacks: qcom_icc_pre_bw_aggregate() is used to clean up bucket values before aggregate bandwidth requests, and qcom_icc_bw_aggregate() is to aggregate bandwidth for buckets. Signed-off-by: Leo Yan Link: https://lore.kernel.org/r/20220712015929.2789881-5-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 51 ++++++++++++++++++++++++++++- drivers/interconnect/qcom/icc-rpm.h | 6 ++++ 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 8c9d5cc7276c..d27b1582521f 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -254,6 +254,54 @@ static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn, return 0; } +/** + * qcom_icc_pre_bw_aggregate - cleans up values before re-aggregate requests + * @node: icc node to operate on + */ +static void qcom_icc_pre_bw_aggregate(struct icc_node *node) +{ + struct qcom_icc_node *qn; + size_t i; + + qn = node->data; + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + qn->sum_avg[i] = 0; + qn->max_peak[i] = 0; + } +} + +/** + * qcom_icc_bw_aggregate - aggregate bw for buckets indicated by tag + * @node: node to aggregate + * @tag: tag to indicate which buckets to aggregate + * @avg_bw: new bw to sum aggregate + * @peak_bw: new bw to max aggregate + * @agg_avg: existing aggregate avg bw val + * @agg_peak: existing aggregate peak bw val + */ +static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + size_t i; + struct qcom_icc_node *qn; + + qn = node->data; + + if (!tag) + tag = QCOM_ICC_TAG_ALWAYS; + + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + if (tag & BIT(i)) { + qn->sum_avg[i] += avg_bw; + qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw); + } + } + + *agg_avg += avg_bw; + *agg_peak = max_t(u32, *agg_peak, peak_bw); + return 0; +} + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; @@ -414,7 +462,8 @@ int qnoc_probe(struct platform_device *pdev) INIT_LIST_HEAD(&provider->nodes); provider->dev = dev; provider->set = qcom_icc_set; - provider->aggregate = icc_std_aggregate; + provider->pre_aggregate = qcom_icc_pre_bw_aggregate; + provider->aggregate = qcom_icc_bw_aggregate; provider->xlate_extended = qcom_icc_xlate_extended; provider->data = data; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index ebee9009301e..a49af844ab13 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -6,6 +6,8 @@ #ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H #define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H +#include + #define RPM_BUS_MASTER_REQ 0x73616d62 #define RPM_BUS_SLAVE_REQ 0x766c7362 @@ -65,6 +67,8 @@ struct qcom_icc_qos { * @links: an array of nodes where we can go next while traversing * @num_links: the total number of @links * @buswidth: width of the interconnect between a node and the bus (bytes) + * @sum_avg: current sum aggregate value of all avg bw requests + * @max_peak: current max aggregate value of all peak bw requests * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves * @qos: NoC QoS setting parameters @@ -75,6 +79,8 @@ struct qcom_icc_node { const u16 *links; u16 num_links; u16 buswidth; + u64 sum_avg[QCOM_ICC_NUM_BUCKETS]; + u64 max_peak[QCOM_ICC_NUM_BUCKETS]; int mas_rpm_id; int slv_rpm_id; struct qcom_icc_qos qos; From e3305daad62c90068e755cdae36a86ac4f02af22 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 12 Jul 2022 09:59:29 +0800 Subject: [PATCH 14/20] interconnect: qcom: icc-rpm: Set bandwidth and clock for bucket values This commit uses buckets for support bandwidth and clock rates. It introduces a new function qcom_icc_bus_aggregate() to calculate the aggregate average and peak bandwidths for every bucket, and also it calculates the maximum value of aggregated average bandwidth across all buckets. The maximum aggregated average is used to calculate the final bandwidth requests. And we can set the clock rate per bucket, we use SLEEP bucket as default bucket if a platform doesn't enable the interconnect path tags in DT binding; otherwise, we use WAKE bucket to set active clock and use SLEEP bucket for other clocks. So far we don't use AMC bucket. Signed-off-by: Leo Yan Link: https://lore.kernel.org/r/20220712015929.2789881-6-leo.yan@linaro.org Signed-off-by: Georgi Djakov --- drivers/interconnect/qcom/icc-rpm.c | 75 +++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index d27b1582521f..7f6a70e0256a 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -302,18 +302,57 @@ static int qcom_icc_bw_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, return 0; } +/** + * qcom_icc_bus_aggregate - aggregate bandwidth by traversing all nodes + * @provider: generic interconnect provider + * @agg_avg: an array for aggregated average bandwidth of buckets + * @agg_peak: an array for aggregated peak bandwidth of buckets + * @max_agg_avg: pointer to max value of aggregated average bandwidth + */ +static void qcom_icc_bus_aggregate(struct icc_provider *provider, + u64 *agg_avg, u64 *agg_peak, + u64 *max_agg_avg) +{ + struct icc_node *node; + struct qcom_icc_node *qn; + int i; + + /* Initialise aggregate values */ + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + agg_avg[i] = 0; + agg_peak[i] = 0; + } + + *max_agg_avg = 0; + + /* + * Iterate nodes on the interconnect and aggregate bandwidth + * requests for every bucket. + */ + list_for_each_entry(node, &provider->nodes, node_list) { + qn = node->data; + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) { + agg_avg[i] += qn->sum_avg[i]; + agg_peak[i] = max_t(u64, agg_peak[i], qn->max_peak[i]); + } + } + + /* Find maximum values across all buckets */ + for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) + *max_agg_avg = max_t(u64, *max_agg_avg, agg_avg[i]); +} + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL; struct icc_provider *provider; - struct icc_node *n; u64 sum_bw; - u64 max_peak_bw; u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; + u64 agg_avg[QCOM_ICC_NUM_BUCKETS], agg_peak[QCOM_ICC_NUM_BUCKETS]; + u64 max_agg_avg; int ret, i; + int bucket; src_qn = src->data; if (dst) @@ -321,12 +360,9 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) provider = src->provider; qp = to_qcom_provider(provider); - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); + qcom_icc_bus_aggregate(provider, agg_avg, agg_peak, &max_agg_avg); - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); + sum_bw = icc_units_to_bps(max_agg_avg); ret = __qcom_icc_set(src, src_qn, sum_bw); if (ret) @@ -337,12 +373,23 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) return ret; } - rate = max(sum_bw, max_peak_bw); - - do_div(rate, src_qn->buswidth); - rate = min_t(u64, rate, LONG_MAX); - for (i = 0; i < qp->num_clks; i++) { + /* + * Use WAKE bucket for active clock, otherwise, use SLEEP bucket + * for other clocks. If a platform doesn't set interconnect + * path tags, by default use sleep bucket for all clocks. + * + * Note, AMC bucket is not supported yet. + */ + if (!strcmp(qp->bus_clks[i].id, "bus_a")) + bucket = QCOM_ICC_BUCKET_WAKE; + else + bucket = QCOM_ICC_BUCKET_SLEEP; + + rate = icc_units_to_bps(max(agg_avg[bucket], agg_peak[bucket])); + do_div(rate, src_qn->buswidth); + rate = min_t(u64, rate, LONG_MAX); + if (qp->bus_clk_rate[i] == rate) continue; From bd734481e172b4827af09c9ab06c51d2ab7201e6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:26 +0800 Subject: [PATCH 15/20] interconnect: imx: fix max_node_id max_node_id not equal to the ARRAY_SIZE of node array, need increase 1, otherwise xlate will fail for the last entry. And rename max_node_id to num_nodes to reflect the reality. Fixes: f0d8048525d7d ("interconnect: Add imx core driver") Reviewed-by: Laurent Pinchart Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-5-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c index 249ca25d1d55..4406ec45fa90 100644 --- a/drivers/interconnect/imx/imx.c +++ b/drivers/interconnect/imx/imx.c @@ -234,16 +234,16 @@ int imx_icc_register(struct platform_device *pdev, struct device *dev = &pdev->dev; struct icc_onecell_data *data; struct icc_provider *provider; - int max_node_id; + int num_nodes; int ret; /* icc_onecell_data is indexed by node_id, unlike nodes param */ - max_node_id = get_max_node_id(nodes, nodes_count); - data = devm_kzalloc(dev, struct_size(data, nodes, max_node_id), + num_nodes = get_max_node_id(nodes, nodes_count) + 1; + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); if (!data) return -ENOMEM; - data->num_nodes = max_node_id; + data->num_nodes = num_nodes; provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); if (!provider) From 6eeaf28c798541e97da0ab7c42b537836de082e0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:27 +0800 Subject: [PATCH 16/20] interconnect: imx: set src node When set QoS for a icc path, only set dst icc node is not enough, also need to set src icc node. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-6-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c index 4406ec45fa90..9b83f69945d8 100644 --- a/drivers/interconnect/imx/imx.c +++ b/drivers/interconnect/imx/imx.c @@ -61,6 +61,12 @@ static int imx_icc_node_set(struct icc_node *node) static int imx_icc_set(struct icc_node *src, struct icc_node *dst) { + int ret; + + ret = imx_icc_node_set(src); + if (ret) + return ret; + return imx_icc_node_set(dst); } From 12db59e8e0a2472307f47586f7767054a46d95f5 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:28 +0800 Subject: [PATCH 17/20] interconnect: imx: introduce imx_icc_provider Introduce imx_icc_provider as a wrapper of icc_provider to add i.MX specific information. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-7-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.c | 24 ++++++++++++++---------- drivers/interconnect/imx/imx.h | 6 ++++++ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c index 9b83f69945d8..1f16eedea21c 100644 --- a/drivers/interconnect/imx/imx.c +++ b/drivers/interconnect/imx/imx.c @@ -134,9 +134,10 @@ static int imx_icc_node_init_qos(struct icc_provider *provider, DEV_PM_QOS_MIN_FREQUENCY, 0); } -static struct icc_node *imx_icc_node_add(struct icc_provider *provider, +static struct icc_node *imx_icc_node_add(struct imx_icc_provider *imx_provider, const struct imx_icc_node_desc *node_desc) { + struct icc_provider *provider = &imx_provider->provider; struct device *dev = provider->dev; struct imx_icc_node *node_data; struct icc_node *node; @@ -184,10 +185,11 @@ static void imx_icc_unregister_nodes(struct icc_provider *provider) imx_icc_node_destroy(node); } -static int imx_icc_register_nodes(struct icc_provider *provider, +static int imx_icc_register_nodes(struct imx_icc_provider *imx_provider, const struct imx_icc_node_desc *descs, int count) { + struct icc_provider *provider = &imx_provider->provider; struct icc_onecell_data *provider_data = provider->data; int ret; int i; @@ -197,7 +199,7 @@ static int imx_icc_register_nodes(struct icc_provider *provider, const struct imx_icc_node_desc *node_desc = &descs[i]; size_t j; - node = imx_icc_node_add(provider, node_desc); + node = imx_icc_node_add(imx_provider, node_desc); if (IS_ERR(node)) { ret = dev_err_probe(provider->dev, PTR_ERR(node), "failed to add %s\n", node_desc->name); @@ -239,6 +241,7 @@ int imx_icc_register(struct platform_device *pdev, { struct device *dev = &pdev->dev; struct icc_onecell_data *data; + struct imx_icc_provider *imx_provider; struct icc_provider *provider; int num_nodes; int ret; @@ -251,16 +254,17 @@ int imx_icc_register(struct platform_device *pdev, return -ENOMEM; data->num_nodes = num_nodes; - provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); - if (!provider) + imx_provider = devm_kzalloc(dev, sizeof(*imx_provider), GFP_KERNEL); + if (!imx_provider) return -ENOMEM; + provider = &imx_provider->provider; provider->set = imx_icc_set; provider->get_bw = imx_icc_get_bw; provider->aggregate = icc_std_aggregate; provider->xlate = of_icc_xlate_onecell; provider->data = data; provider->dev = dev->parent; - platform_set_drvdata(pdev, provider); + platform_set_drvdata(pdev, imx_provider); ret = icc_provider_add(provider); if (ret) { @@ -268,7 +272,7 @@ int imx_icc_register(struct platform_device *pdev, return ret; } - ret = imx_icc_register_nodes(provider, nodes, nodes_count); + ret = imx_icc_register_nodes(imx_provider, nodes, nodes_count); if (ret) goto provider_del; @@ -282,11 +286,11 @@ EXPORT_SYMBOL_GPL(imx_icc_register); int imx_icc_unregister(struct platform_device *pdev) { - struct icc_provider *provider = platform_get_drvdata(pdev); + struct imx_icc_provider *imx_provider = platform_get_drvdata(pdev); - imx_icc_unregister_nodes(provider); + imx_icc_unregister_nodes(&imx_provider->provider); - return icc_provider_del(provider); + return icc_provider_del(&imx_provider->provider); } EXPORT_SYMBOL_GPL(imx_icc_unregister); diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 75da51076c68..0ad2c654c222 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -10,10 +10,16 @@ #ifndef __DRIVERS_INTERCONNECT_IMX_H #define __DRIVERS_INTERCONNECT_IMX_H +#include #include #define IMX_ICC_MAX_LINKS 4 +struct imx_icc_provider { + void __iomem *noc_base; + struct icc_provider provider; +}; + /* * struct imx_icc_node_adj - Describe a dynamic adjustable node */ From 7980d85a9443029c39a9d131c13732258e44a8de Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:29 +0800 Subject: [PATCH 18/20] interconnect: imx: configure NoC mode/prioriry/ext_control Introduce imx_icc_noc_setting structure to describe a master port setting Pass imx_icc_noc_setting as a parameter from specific driver Set priority level, mode, ext control in imx_icc_node_set Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-8-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/imx.c | 50 +++++++++++++++++++++++++++---- drivers/interconnect/imx/imx.h | 43 +++++++++++++++++++++++++- drivers/interconnect/imx/imx8mm.c | 2 +- drivers/interconnect/imx/imx8mn.c | 2 +- drivers/interconnect/imx/imx8mq.c | 2 +- 5 files changed, 90 insertions(+), 9 deletions(-) diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c index 1f16eedea21c..48ffd59953bf 100644 --- a/drivers/interconnect/imx/imx.c +++ b/drivers/interconnect/imx/imx.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -21,8 +22,10 @@ /* private icc_node data */ struct imx_icc_node { const struct imx_icc_node_desc *desc; + const struct imx_icc_noc_setting *setting; struct device *qos_dev; struct dev_pm_qos_request qos_req; + struct imx_icc_provider *imx_provider; }; static int imx_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak) @@ -37,8 +40,30 @@ static int imx_icc_node_set(struct icc_node *node) { struct device *dev = node->provider->dev; struct imx_icc_node *node_data = node->data; + void __iomem *base; + u32 prio; u64 freq; + if (node_data->setting && node->peak_bw) { + base = node_data->setting->reg + node_data->imx_provider->noc_base; + if (node_data->setting->mode == IMX_NOC_MODE_FIXED) { + prio = node_data->setting->prio_level; + prio = PRIORITY_COMP_MARK | (prio << 8) | prio; + writel(prio, base + IMX_NOC_PRIO_REG); + writel(node_data->setting->mode, base + IMX_NOC_MODE_REG); + writel(node_data->setting->ext_control, base + IMX_NOC_EXT_CTL_REG); + dev_dbg(dev, "%s: mode: 0x%x, prio: 0x%x, ext_control: 0x%x\n", + node_data->desc->name, node_data->setting->mode, prio, + node_data->setting->ext_control); + } else if (node_data->setting->mode == IMX_NOC_MODE_UNCONFIGURED) { + dev_dbg(dev, "%s: mode not unconfigured\n", node_data->desc->name); + } else { + dev_info(dev, "%s: mode: %d not supported\n", + node_data->desc->name, node_data->setting->mode); + return -EOPNOTSUPP; + } + } + if (!node_data->qos_dev) return 0; @@ -135,7 +160,8 @@ static int imx_icc_node_init_qos(struct icc_provider *provider, } static struct icc_node *imx_icc_node_add(struct imx_icc_provider *imx_provider, - const struct imx_icc_node_desc *node_desc) + const struct imx_icc_node_desc *node_desc, + const struct imx_icc_noc_setting *setting) { struct icc_provider *provider = &imx_provider->provider; struct device *dev = provider->dev; @@ -164,6 +190,8 @@ static struct icc_node *imx_icc_node_add(struct imx_icc_provider *imx_provider, node->name = node_desc->name; node->data = node_data; node_data->desc = node_desc; + node_data->setting = setting; + node_data->imx_provider = imx_provider; icc_node_add(node, provider); if (node_desc->adj) { @@ -187,7 +215,8 @@ static void imx_icc_unregister_nodes(struct icc_provider *provider) static int imx_icc_register_nodes(struct imx_icc_provider *imx_provider, const struct imx_icc_node_desc *descs, - int count) + int count, + const struct imx_icc_noc_setting *settings) { struct icc_provider *provider = &imx_provider->provider; struct icc_onecell_data *provider_data = provider->data; @@ -199,7 +228,8 @@ static int imx_icc_register_nodes(struct imx_icc_provider *imx_provider, const struct imx_icc_node_desc *node_desc = &descs[i]; size_t j; - node = imx_icc_node_add(imx_provider, node_desc); + node = imx_icc_node_add(imx_provider, node_desc, + settings ? &settings[node_desc->id] : NULL); if (IS_ERR(node)) { ret = dev_err_probe(provider->dev, PTR_ERR(node), "failed to add %s\n", node_desc->name); @@ -237,7 +267,8 @@ static int get_max_node_id(struct imx_icc_node_desc *nodes, int nodes_count) } int imx_icc_register(struct platform_device *pdev, - struct imx_icc_node_desc *nodes, int nodes_count) + struct imx_icc_node_desc *nodes, int nodes_count, + struct imx_icc_noc_setting *settings) { struct device *dev = &pdev->dev; struct icc_onecell_data *data; @@ -266,13 +297,22 @@ int imx_icc_register(struct platform_device *pdev, provider->dev = dev->parent; platform_set_drvdata(pdev, imx_provider); + if (settings) { + imx_provider->noc_base = devm_of_iomap(dev, provider->dev->of_node, 0, NULL); + if (IS_ERR(imx_provider->noc_base)) { + ret = PTR_ERR(imx_provider->noc_base); + dev_err(dev, "Error mapping NoC: %d\n", ret); + return ret; + } + } + ret = icc_provider_add(provider); if (ret) { dev_err(dev, "error adding interconnect provider: %d\n", ret); return ret; } - ret = imx_icc_register_nodes(imx_provider, nodes, nodes_count); + ret = imx_icc_register_nodes(imx_provider, nodes, nodes_count, settings); if (ret) goto provider_del; diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h index 0ad2c654c222..e0a2ee173ecd 100644 --- a/drivers/interconnect/imx/imx.h +++ b/drivers/interconnect/imx/imx.h @@ -15,6 +15,32 @@ #define IMX_ICC_MAX_LINKS 4 +/* + * High throughput priority level in Regulator mode + * Read Priority in Fixed/Limiter mode + */ +#define PRIORITY0_SHIFT 0 +/* + * Low throughput priority level in Regulator mode + * Write Priority in Fixed/Limiter mode + */ +#define PRIORITY1_SHIFT 8 +#define PRIORITY_MASK 0x7 + +#define PRIORITY_COMP_MARK BIT(31) /* Must set */ + +#define IMX_NOC_MODE_FIXED 0 +#define IMX_NOC_MODE_LIMITER 1 +#define IMX_NOC_MODE_BYPASS 2 +#define IMX_NOC_MODE_REGULATOR 3 +#define IMX_NOC_MODE_UNCONFIGURED 0xFF + +#define IMX_NOC_PRIO_REG 0x8 +#define IMX_NOC_MODE_REG 0xC +#define IMX_NOC_BANDWIDTH_REG 0x10 +#define IMX_NOC_SATURATION 0x14 +#define IMX_NOC_EXT_CTL_REG 0x18 + struct imx_icc_provider { void __iomem *noc_base; struct icc_provider provider; @@ -44,6 +70,20 @@ struct imx_icc_node_desc { const struct imx_icc_node_adj_desc *adj; }; +/* + * struct imx_icc_noc_setting - Describe an interconnect node setting + * @reg: register offset inside the NoC + * @prio_level: priority level + * @mode: functional mode + * @ext_control: external input control + */ +struct imx_icc_noc_setting { + u32 reg; + u32 prio_level; + u32 mode; + u32 ext_control; +}; + #define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \ { \ .id = _id, \ @@ -61,7 +101,8 @@ struct imx_icc_node_desc { int imx_icc_register(struct platform_device *pdev, struct imx_icc_node_desc *nodes, - int nodes_count); + int nodes_count, + struct imx_icc_noc_setting *noc_settings); int imx_icc_unregister(struct platform_device *pdev); #endif /* __DRIVERS_INTERCONNECT_IMX_H */ diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c index 1083490bb391..ae797412db96 100644 --- a/drivers/interconnect/imx/imx8mm.c +++ b/drivers/interconnect/imx/imx8mm.c @@ -83,7 +83,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mm_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mm_icc_remove(struct platform_device *pdev) diff --git a/drivers/interconnect/imx/imx8mn.c b/drivers/interconnect/imx/imx8mn.c index ad97e55fd4e5..1ce94c5bdd8c 100644 --- a/drivers/interconnect/imx/imx8mn.c +++ b/drivers/interconnect/imx/imx8mn.c @@ -72,7 +72,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mn_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mn_icc_remove(struct platform_device *pdev) diff --git a/drivers/interconnect/imx/imx8mq.c b/drivers/interconnect/imx/imx8mq.c index d7768d3c6d8a..7f00a0511c6e 100644 --- a/drivers/interconnect/imx/imx8mq.c +++ b/drivers/interconnect/imx/imx8mq.c @@ -82,7 +82,7 @@ static struct imx_icc_node_desc nodes[] = { static int imx8mq_icc_probe(struct platform_device *pdev) { - return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes)); + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL); } static int imx8mq_icc_remove(struct platform_device *pdev) From c14ec5c93dc8f6e05abee962243bda9dc104567b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:30 +0800 Subject: [PATCH 19/20] interconnect: imx: Add platform driver for imx8mp Add a platform driver for the i.MX8MP SoC describing bus topology, based on internal documentation. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220703091132.1412063-9-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/interconnect/imx/Kconfig | 4 + drivers/interconnect/imx/Makefile | 2 + drivers/interconnect/imx/imx8mp.c | 259 ++++++++++++++++++++++++++++++ 3 files changed, 265 insertions(+) create mode 100644 drivers/interconnect/imx/imx8mp.c diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig index be2928362bb7..c772552431f5 100644 --- a/drivers/interconnect/imx/Kconfig +++ b/drivers/interconnect/imx/Kconfig @@ -15,3 +15,7 @@ config INTERCONNECT_IMX8MN config INTERCONNECT_IMX8MQ tristate "i.MX8MQ interconnect driver" depends on INTERCONNECT_IMX + +config INTERCONNECT_IMX8MP + tristate "i.MX8MP interconnect driver" + depends on INTERCONNECT_IMX diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile index 21fd5233754f..16d256cdeab4 100644 --- a/drivers/interconnect/imx/Makefile +++ b/drivers/interconnect/imx/Makefile @@ -2,8 +2,10 @@ imx-interconnect-objs := imx.o imx8mm-interconnect-objs := imx8mm.o imx8mq-interconnect-objs := imx8mq.o imx8mn-interconnect-objs := imx8mn.o +imx8mp-interconnect-objs := imx8mp.o obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o +obj-$(CONFIG_INTERCONNECT_IMX8MP) += imx8mp-interconnect.o diff --git a/drivers/interconnect/imx/imx8mp.c b/drivers/interconnect/imx/imx8mp.c new file mode 100644 index 000000000000..5f1c83ed157b --- /dev/null +++ b/drivers/interconnect/imx/imx8mp.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Interconnect framework driver for i.MX8MP SoC + * + * Copyright 2022 NXP + * Peng Fan + */ + +#include +#include +#include +#include + +#include "imx.h" + +static const struct imx_icc_node_adj_desc imx8mp_noc_adj = { + .bw_mul = 1, + .bw_div = 16, + .main_noc = true, +}; + +static struct imx_icc_noc_setting noc_setting_nodes[] = { + [IMX8MP_ICM_MLMIX] = { + .reg = 0x180, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_DSP] = { + .reg = 0x200, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_SDMA2PER] = { + .reg = 0x280, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA2BURST] = { + .reg = 0x300, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA3PER] = { + .reg = 0x380, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_SDMA3BURST] = { + .reg = 0x400, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_EDMA] = { + .reg = 0x480, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 4, + }, + [IMX8MP_ICM_GPU3D] = { + .reg = 0x500, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_GPU2D] = { + .reg = 0x580, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_HRV] = { + .reg = 0x600, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_LCDIF_HDMI] = { + .reg = 0x680, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_HDCP] = { + .reg = 0x700, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 5, + }, + [IMX8MP_ICM_NOC_PCIE] = { + .reg = 0x780, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_USB1] = { + .reg = 0x800, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_USB2] = { + .reg = 0x880, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_PCIE] = { + .reg = 0x900, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_LCDIF_RD] = { + .reg = 0x980, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_LCDIF_WR] = { + .reg = 0xa00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI0] = { + .reg = 0xa80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI1] = { + .reg = 0xb00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISI2] = { + .reg = 0xb80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 2, + .ext_control = 1, + }, + [IMX8MP_ICM_ISP0] = { + .reg = 0xc00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_ISP1] = { + .reg = 0xc80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_DWE] = { + .reg = 0xd00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 7, + }, + [IMX8MP_ICM_VPU_G1] = { + .reg = 0xd80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_VPU_G2] = { + .reg = 0xe00, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICM_VPU_H1] = { + .reg = 0xe80, + .mode = IMX_NOC_MODE_FIXED, + .prio_level = 3, + }, + [IMX8MP_ICN_MEDIA] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_VIDEO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_AUDIO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_HDMI] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_GPU] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, + [IMX8MP_ICN_HSIO] = { + .mode = IMX_NOC_MODE_UNCONFIGURED, + }, +}; + +/* Describe bus masters, slaves and connections between them */ +static struct imx_icc_node_desc nodes[] = { + DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj, + IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN), + + DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL), + DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL), + DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC), + + DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO), + DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO), + + DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU), + DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU), + + DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI), + DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI), + DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI), + + DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO), + DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO), + + DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA), + DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA), + + DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC), + DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO), + DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO), + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL, + IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM), +}; + +static int imx8mp_icc_probe(struct platform_device *pdev) +{ + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes); +} + +static int imx8mp_icc_remove(struct platform_device *pdev) +{ + return imx_icc_unregister(pdev); +} + +static struct platform_driver imx8mp_icc_driver = { + .probe = imx8mp_icc_probe, + .remove = imx8mp_icc_remove, + .driver = { + .name = "imx8mp-interconnect", + }, +}; + +module_platform_driver(imx8mp_icc_driver); +MODULE_AUTHOR("Peng Fan "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:imx8mp-interconnect"); From 9760660e866d643817c3bf21e6dc20837a1052c4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 3 Jul 2022 17:11:31 +0800 Subject: [PATCH 20/20] PM / devfreq: imx: Register i.MX8MP interconnect device Same to i.MX8MM/N/Q, register i.MX8MP interconnect device to make i.MX8MP Interconnect driver work. Signed-off-by: Peng Fan Acked-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220703091132.1412063-10-peng.fan@oss.nxp.com Signed-off-by: Georgi Djakov --- drivers/devfreq/imx-bus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/devfreq/imx-bus.c b/drivers/devfreq/imx-bus.c index f3f6e25053ed..afb552198937 100644 --- a/drivers/devfreq/imx-bus.c +++ b/drivers/devfreq/imx-bus.c @@ -145,6 +145,7 @@ static const struct of_device_id imx_bus_of_match[] = { { .compatible = "fsl,imx8mq-noc", .data = "imx8mq-interconnect", }, { .compatible = "fsl,imx8mm-noc", .data = "imx8mm-interconnect", }, { .compatible = "fsl,imx8mn-noc", .data = "imx8mn-interconnect", }, + { .compatible = "fsl,imx8mp-noc", .data = "imx8mp-interconnect", }, { .compatible = "fsl,imx8m-noc", }, { .compatible = "fsl,imx8m-nic", }, { /* sentinel */ },