mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-13 14:14:37 +00:00
Code Issues Releases Wiki Activity

staging: comedi: drivers: re-do PLX PCI 9080 DMAMODEx register values

Browse source 
Replace the existing macros in "plx9080.h" that define values for the
DMAMODE0 and DMAMODE1 registers.  Use the prefix `PLX_DMAMODE_` for the
macros.  Make use of the `BIT(x)` and `GENMASK(h,l)` macros to define
the values.

Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott 2016-05-20 14:49:16 +01:00 committed by Greg Kroah-Hartman
parent df04d3aa02
commit 65bf53de83
3 changed files with 53 additions and 35 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
drivers/staging/comedi/drivers/cb_pcidas64.c
View file

@ -1308,28 +1308,28 @@ static void init_plx9080(struct comedi_device *dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input, not sure if this is necessary */
bits |= PLX_DMA_EN_READYIN_BIT;
bits |= PLX_DMAMODE_READYIEN;
/* enable bterm, not sure if this is necessary */
bits |= PLX_EN_BTERM_BIT;
bits |= PLX_DMAMODE_BTERMIEN;
/* enable dma chaining */
bits |= PLX_EN_CHAIN_BIT;
bits |= PLX_DMAMODE_CHAINEN;
/* enable interrupt on dma done
* (probably don't need this, since chain never finishes) */
bits |= PLX_EN_DMA_DONE_INTR_BIT;
bits |= PLX_DMAMODE_DONEIEN;
/* don't increment local address during transfers
* (we are transferring from a fixed fifo register) */
bits |= PLX_LOCAL_ADDR_CONST_BIT;
bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
bits |= PLX_DMA_INTR_PCI_BIT;
bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
bits |= PLX_DEMAND_MODE_BIT;
bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
bits |= PLX_DMAMODE_BURSTEN;
/* 4020 uses 32 bit dma */
if (board->layout == LAYOUT_4020)
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
bits |= PLX_DMAMODE_WIDTH32;
else /* localspace0 bus is 16 bits wide */
bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
bits |= PLX_DMAMODE_WIDTH16;
writel(bits, plx_iobase + PLX_REG_DMAMODE1);
if (ao_cmd_is_supported(board))
writel(bits, plx_iobase + PLX_REG_DMAMODE0);

16
drivers/staging/comedi/drivers/gsc_hpdi.c
View file

@ -563,26 +563,26 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
/* configure dma0 mode */
bits = 0;
/* enable ready input */
bits |= PLX_DMA_EN_READYIN_BIT;
bits |= PLX_DMAMODE_READYIEN;
/* enable dma chaining */
bits |= PLX_EN_CHAIN_BIT;
bits |= PLX_DMAMODE_CHAINEN;
/*
* enable interrupt on dma done
* (probably don't need this, since chain never finishes)
*/
bits |= PLX_EN_DMA_DONE_INTR_BIT;
bits |= PLX_DMAMODE_DONEIEN;
/*
* don't increment local address during transfers
* (we are transferring from a fixed fifo register)
*/
bits |= PLX_LOCAL_ADDR_CONST_BIT;
bits |= PLX_DMAMODE_LACONST;
/* route dma interrupt to pci bus */
bits |= PLX_DMA_INTR_PCI_BIT;
bits |= PLX_DMAMODE_INTRPCI;
/* enable demand mode */
bits |= PLX_DEMAND_MODE_BIT;
bits |= PLX_DMAMODE_DEMAND;
/* enable local burst mode */
bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
bits |= PLX_DMAMODE_BURSTEN;
bits |= PLX_DMAMODE_WIDTH32;
writel(bits, plx_iobase + PLX_REG_DMAMODE0);
}

52
drivers/staging/comedi/drivers/plx9080.h
View file

@ -457,23 +457,41 @@ struct plx_dma_desc {
#define PLX_REG_DMAMODE0 0x0080
#define PLX_REG_DMAMODE1 0x0094
#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1
#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3
#define PLX_LOCAL_BUS_WIDTH_MASK 0x3
#define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */
#define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */
#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */
#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */
/* enables interrupt on dma done */
#define PLX_EN_DMA_DONE_INTR_BIT 0x400
/* hold local address constant (don't increment) */
#define PLX_LOCAL_ADDR_CONST_BIT 0x800
/* enables demand-mode for dma transfer */
#define PLX_DEMAND_MODE_BIT 0x1000
#define PLX_EOT_ENABLE_BIT 0x4000
#define PLX_STOP_MODE_BIT 0x8000
/* routes dma interrupt to pci bus (instead of local bus) */
#define PLX_DMA_INTR_PCI_BIT 0x20000
/* Local Bus Width */
#define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */
#define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */
#define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */
#define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */
#define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0)
#define PLX_DMAMODE_WIDTH_SHIFT 0
/* Internal Wait States */
#define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf))
#define PLX_DMAMODE_IWS_MASK GENMASK(5, 2)
#define PLX_DMAMODE_SHIFT 2
/* Ready Input Enable */
#define PLX_DMAMODE_READYIEN BIT(6)
/* BTERM# Input Enable */
#define PLX_DMAMODE_BTERMIEN BIT(7)
/* Local Burst Enable */
#define PLX_DMAMODE_BURSTEN BIT(8)
/* Chaining Enable */
#define PLX_DMAMODE_CHAINEN BIT(9)
/* Done Interrupt Enable */
#define PLX_DMAMODE_DONEIEN BIT(10)
/* Hold Local Address Constant */
#define PLX_DMAMODE_LACONST BIT(11)
/* Demand Mode */
#define PLX_DMAMODE_DEMAND BIT(12)
/* Write And Invalidate Mode */
#define PLX_DMAMODE_WINVALIDATE BIT(13)
/* DMA EOT Enable - enables EOT0# or EOT1# input pin */
#define PLX_DMAMODE_EOTEN BIT(14)
/* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
#define PLX_DMAMODE_STOP BIT(15)
/* DMA Clear Count Mode - count in descriptor cleared on completion */
#define PLX_DMAMODE_CLRCOUNT BIT(16)
/* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
#define PLX_DMAMODE_INTRPCI BIT(17)
/* DMA Channel N PCI Address Register (N <= 1) */
#define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)