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media: sun4i-csi: Fix data sampling polarity handling
[ Upstream commitcf9e6d5dbd
] The CLK_POL field specifies whether data is sampled on the falling or rising edge of PCLK, not whether the data lines are active high or low. Evidence of this can be found in the timing diagram labeled "horizontal size setting and pixel clock timing". Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING. While at it, reorder the three polarity flag checks so HSYNC and VSYNC are grouped together. Fixes:577bbf23b7
("media: sunxi: Add A10 CSI driver") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 1 additions and 1 deletions
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@ -279,8 +279,8 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
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csi->regs + CSI_WIN_CTRL_H_REG);
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hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
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pclk_pol = !!(bus->flags & V4L2_MBUS_DATA_ACTIVE_HIGH);
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vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
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pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);
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writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
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CSI_CFG_OUTPUT_FMT(csi_fmt->output) |
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CSI_CFG_VSYNC_POL(vsync_pol) |
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