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amd64_edac: fix DRAM base and limit extraction
On Fam10h and above, F1x[1, 0][7C:40] are DRAM Base/Limit registers which specify the destination node of a DRAM address. Those address boundaries are being extracted into ->dram_base[] and ->dram_limit[]. Correct the extraction masks to match the respective address bits. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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9d858bb10a
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66216a7a15
1 changed files with 5 additions and 5 deletions
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@ -1368,8 +1368,8 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
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pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) |
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((u64) low_base & 0xFFFF0000))) << 8;
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pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
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(((u64)low_base & 0xFFFF0000) << 24);
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low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
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high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
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@ -1390,9 +1390,9 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
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* Extract address values and form a LIMIT address. Limit is the HIGHEST
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* memory location of the region, so low 24 bits need to be all ones.
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*/
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low_limit |= 0x0000FFFF;
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pvt->dram_limit[dram] =
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((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF);
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pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
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(((u64) low_limit & 0xFFFF0000) << 24) |
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0x00FFFFFF;
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}
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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