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net: arc: trivial: cleanup the emac driver
This patch will make the driver more readability The emac has the error and warnings if you run 'scripts/checkpatch.pl -f --subjective xxx' to check. Let's clean up such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Jiri Kosina <trivial@kernel.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Alexander Kochetkov <al.kochet@gmail.com> Cc: netdev@vger.kernel.org Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
1bddd96cba
commit
663713eb47
4 changed files with 75 additions and 57 deletions
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@ -14,36 +14,36 @@
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#include <linux/clk.h>
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/* STATUS and ENABLE Register bit masks */
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#define TXINT_MASK (1<<0) /* Transmit interrupt */
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#define RXINT_MASK (1<<1) /* Receive interrupt */
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#define ERR_MASK (1<<2) /* Error interrupt */
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#define TXCH_MASK (1<<3) /* Transmit chaining error interrupt */
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#define MSER_MASK (1<<4) /* Missed packet counter error */
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#define RXCR_MASK (1<<8) /* RXCRCERR counter rolled over */
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#define RXFR_MASK (1<<9) /* RXFRAMEERR counter rolled over */
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#define RXFL_MASK (1<<10) /* RXOFLOWERR counter rolled over */
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#define MDIO_MASK (1<<12) /* MDIO complete interrupt */
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#define TXPL_MASK (1<<31) /* Force polling of BD by EMAC */
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#define TXINT_MASK (1 << 0) /* Transmit interrupt */
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#define RXINT_MASK (1 << 1) /* Receive interrupt */
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#define ERR_MASK (1 << 2) /* Error interrupt */
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#define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
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#define MSER_MASK (1 << 4) /* Missed packet counter error */
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#define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
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#define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
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#define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
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#define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
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#define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
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/* CONTROL Register bit masks */
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#define EN_MASK (1<<0) /* VMAC enable */
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#define TXRN_MASK (1<<3) /* TX enable */
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#define RXRN_MASK (1<<4) /* RX enable */
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#define DSBC_MASK (1<<8) /* Disable receive broadcast */
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#define ENFL_MASK (1<<10) /* Enable Full-duplex */
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#define PROM_MASK (1<<11) /* Promiscuous mode */
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#define EN_MASK (1 << 0) /* VMAC enable */
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#define TXRN_MASK (1 << 3) /* TX enable */
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#define RXRN_MASK (1 << 4) /* RX enable */
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#define DSBC_MASK (1 << 8) /* Disable receive broadcast */
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#define ENFL_MASK (1 << 10) /* Enable Full-duplex */
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#define PROM_MASK (1 << 11) /* Promiscuous mode */
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/* Buffer descriptor INFO bit masks */
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#define OWN_MASK (1<<31) /* 0-CPU owns buffer, 1-EMAC owns buffer */
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#define FIRST_MASK (1<<16) /* First buffer in chain */
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#define LAST_MASK (1<<17) /* Last buffer in chain */
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#define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
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#define FIRST_MASK (1 << 16) /* First buffer in chain */
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#define LAST_MASK (1 << 17) /* Last buffer in chain */
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#define LEN_MASK 0x000007FF /* last 11 bits */
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#define CRLS (1<<21)
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#define DEFR (1<<22)
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#define DROP (1<<23)
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#define RTRY (1<<24)
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#define LTCL (1<<28)
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#define UFLO (1<<29)
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#define CRLS (1 << 21)
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#define DEFR (1 << 22)
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#define DROP (1 << 23)
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#define RTRY (1 << 24)
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#define LTCL (1 << 28)
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#define UFLO (1 << 29)
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#define FOR_EMAC OWN_MASK
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#define FOR_CPU 0
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@ -66,7 +66,7 @@ enum {
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R_MDIO,
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};
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#define TX_TIMEOUT (400*HZ/1000) /* Transmission timeout */
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#define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
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#define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
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@ -196,6 +196,7 @@ static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
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static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value | mask);
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}
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@ -211,6 +212,7 @@ static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
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static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
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{
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unsigned int value = arc_reg_get(priv, reg);
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arc_reg_set(priv, reg, value & ~mask);
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}
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@ -26,7 +26,6 @@
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#include "emac.h"
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/**
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* arc_emac_tx_avail - Return the number of available slots in the tx ring.
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* @priv: Pointer to ARC EMAC private data structure.
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@ -66,7 +65,7 @@ static void arc_emac_adjust_link(struct net_device *ndev)
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if (priv->duplex != phy_dev->duplex) {
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reg = arc_reg_get(priv, R_CTRL);
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if (DUPLEX_FULL == phy_dev->duplex)
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if (phy_dev->duplex == DUPLEX_FULL)
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reg |= ENFL_MASK;
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else
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reg &= ~ENFL_MASK;
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@ -466,9 +465,9 @@ static int arc_emac_open(struct net_device *ndev)
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/* Set CONTROL */
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arc_reg_set(priv, R_CTRL,
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(RX_BD_NUM << 24) | /* RX BD table length */
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(TX_BD_NUM << 16) | /* TX BD table length */
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TXRN_MASK | RXRN_MASK);
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(RX_BD_NUM << 24) | /* RX BD table length */
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(TX_BD_NUM << 16) | /* TX BD table length */
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TXRN_MASK | RXRN_MASK);
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napi_enable(&priv->napi);
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@ -533,8 +532,10 @@ static void arc_free_tx_queue(struct net_device *ndev)
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struct buffer_state *tx_buff = &priv->tx_buff[i];
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if (tx_buff->skb) {
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dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
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dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
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dma_unmap_single(&ndev->dev,
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dma_unmap_addr(tx_buff, addr),
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dma_unmap_len(tx_buff, len),
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DMA_TO_DEVICE);
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/* return the sk_buff to system */
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dev_kfree_skb_irq(tx_buff->skb);
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@ -562,8 +563,10 @@ static void arc_free_rx_queue(struct net_device *ndev)
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struct buffer_state *rx_buff = &priv->rx_buff[i];
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if (rx_buff->skb) {
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dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
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dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
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dma_unmap_single(&ndev->dev,
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dma_unmap_addr(rx_buff, addr),
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dma_unmap_len(rx_buff, len),
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DMA_FROM_DEVICE);
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/* return the sk_buff to system */
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dev_kfree_skb_irq(rx_buff->skb);
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@ -717,8 +720,8 @@ static void arc_emac_set_address_internal(struct net_device *ndev)
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struct arc_emac_priv *priv = netdev_priv(ndev);
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unsigned int addr_low, addr_hi;
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addr_low = le32_to_cpu(*(__le32 *) &ndev->dev_addr[0]);
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addr_hi = le16_to_cpu(*(__le16 *) &ndev->dev_addr[4]);
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addr_low = le32_to_cpu(*(__le32 *)&ndev->dev_addr[0]);
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addr_hi = le16_to_cpu(*(__le16 *)&ndev->dev_addr[4]);
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arc_reg_set(priv, R_ADDRL, addr_low);
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arc_reg_set(priv, R_ADDRH, addr_hi);
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@ -774,7 +777,6 @@ int arc_emac_probe(struct net_device *ndev, int interface)
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unsigned int id, clock_frequency, irq;
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int err;
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/* Get PHY from device tree */
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phy_node = of_parse_phandle(dev->of_node, "phy", 0);
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if (!phy_node) {
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@ -796,7 +798,6 @@ int arc_emac_probe(struct net_device *ndev, int interface)
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return -ENODEV;
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}
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ndev->netdev_ops = &arc_emac_netdev_ops;
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ndev->ethtool_ops = &arc_emac_ethtool_ops;
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ndev->watchdog_timeo = TX_TIMEOUT;
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@ -807,9 +808,9 @@ int arc_emac_probe(struct net_device *ndev, int interface)
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priv->dev = dev;
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priv->regs = devm_ioremap_resource(dev, &res_regs);
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if (IS_ERR(priv->regs)) {
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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}
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dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
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if (priv->clk) {
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@ -930,10 +931,8 @@ int arc_emac_remove(struct net_device *ndev)
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unregister_netdev(ndev);
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netif_napi_del(&priv->napi);
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if (!IS_ERR(priv->clk)) {
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if (!IS_ERR(priv->clk))
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clk_disable_unprepare(priv->clk);
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}
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return 0;
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}
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@ -94,7 +94,7 @@ static int arc_mdio_write(struct mii_bus *bus, int phy_addr,
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phy_addr, reg_num, value);
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arc_reg_set(priv, R_MDIO,
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0x50020000 | (phy_addr << 23) | (reg_num << 18) | value);
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0x50020000 | (phy_addr << 23) | (reg_num << 18) | value);
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return arc_mdio_complete_wait(priv);
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}
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@ -50,7 +50,7 @@ static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
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u32 data;
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int err = 0;
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switch(speed) {
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switch (speed) {
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case 10:
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data = (1 << (speed_offset + 16)) | (0 << speed_offset);
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break;
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};
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static const struct of_device_id emac_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3036-emac", .data = &emac_rk3036_emac_data },
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{ .compatible = "rockchip,rk3066-emac", .data = &emac_rk3066_emac_data },
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{ .compatible = "rockchip,rk3188-emac", .data = &emac_rk3188_emac_data },
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{
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.compatible = "rockchip,rk3036-emac",
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.data = &emac_rk3036_emac_data,
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},
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{
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.compatible = "rockchip,rk3066-emac",
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.data = &emac_rk3066_emac_data,
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},
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{
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.compatible = "rockchip,rk3188-emac",
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.data = &emac_rk3188_emac_data,
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},
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{ /* Sentinel */ }
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};
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@ -123,9 +132,11 @@ static int emac_rockchip_probe(struct platform_device *pdev)
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goto out_netdev;
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}
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priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
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priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,grf");
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if (IS_ERR(priv->grf)) {
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dev_err(dev, "failed to retrieve global register file (%ld)\n", PTR_ERR(priv->grf));
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dev_err(dev, "failed to retrieve global register file (%ld)\n",
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PTR_ERR(priv->grf));
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err = PTR_ERR(priv->grf);
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goto out_netdev;
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}
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priv->emac.clk = devm_clk_get(dev, "hclk");
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if (IS_ERR(priv->emac.clk)) {
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dev_err(dev, "failed to retrieve host clock (%ld)\n", PTR_ERR(priv->emac.clk));
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dev_err(dev, "failed to retrieve host clock (%ld)\n",
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PTR_ERR(priv->emac.clk));
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err = PTR_ERR(priv->emac.clk);
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goto out_netdev;
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}
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priv->refclk = devm_clk_get(dev, "macref");
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if (IS_ERR(priv->refclk)) {
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dev_err(dev, "failed to retrieve reference clock (%ld)\n", PTR_ERR(priv->refclk));
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dev_err(dev, "failed to retrieve reference clock (%ld)\n",
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PTR_ERR(priv->refclk));
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err = PTR_ERR(priv->refclk);
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goto out_netdev;
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}
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@ -179,19 +192,22 @@ static int emac_rockchip_probe(struct platform_device *pdev)
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err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
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if (err) {
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dev_err(dev, "unable to apply initial settings to grf (%d)\n", err);
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dev_err(dev, "unable to apply initial settings to grf (%d)\n",
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err);
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goto out_regulator_disable;
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}
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/* RMII interface needs always a rate of 50MHz */
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err = clk_set_rate(priv->refclk, 50000000);
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if (err)
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dev_err(dev, "failed to change reference clock rate (%d)\n", err);
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dev_err(dev,
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"failed to change reference clock rate (%d)\n", err);
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if (priv->soc_data->need_div_macclk) {
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priv->macclk = devm_clk_get(dev, "macclk");
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if (IS_ERR(priv->macclk)) {
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dev_err(dev, "failed to retrieve mac clock (%ld)\n", PTR_ERR(priv->macclk));
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dev_err(dev, "failed to retrieve mac clock (%ld)\n",
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PTR_ERR(priv->macclk));
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err = PTR_ERR(priv->macclk);
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goto out_regulator_disable;
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}
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/* RMII TX/RX needs always a rate of 25MHz */
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err = clk_set_rate(priv->macclk, 25000000);
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if (err)
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dev_err(dev, "failed to change mac clock rate (%d)\n", err);
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dev_err(dev,
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"failed to change mac clock rate (%d)\n", err);
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}
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err = arc_emac_probe(ndev, interface);
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