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dt-bindings: reset: mt8195: add vdosys1 reset control bit 

Add vdosys1 reset control bit for MT8195 platform.

Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230113104434.28023-3-nancy.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Nancy.Lin 2023-01-13 18:44:25 +08:00 committed by Matthias Brugger
parent 82219cfbef
commit 664a39b8e7
1 changed files with 45 additions and 0 deletions
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45
include/dt-bindings/reset/mt8195-resets.h
View File

@ -35,4 +35,49 @@
#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5
/* VDOSYS1 */
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */