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dt-bindings: reset: mt8195: add vdosys1 reset control bit
Add vdosys1 reset control bit for MT8195 platform. Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230113104434.28023-3-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
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#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5
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/* VDOSYS1 */
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#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
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#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
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#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
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#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
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#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
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#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
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#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
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#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
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#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
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#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
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#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
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#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
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#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
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#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
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#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
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#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
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#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
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#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
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#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
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#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
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#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
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#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
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#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
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#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
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#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
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#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
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#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
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