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MIPS: OCTEON: Implement the core-16057 workaround
Disable ICache prefetch for certian Octeon II processors. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8938/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -63,6 +63,28 @@
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li v1, ~(7 << 7)
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and v0, v0, v1
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ori v0, v0, (6 << 7)
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mfc0 v1, CP0_PRID_REG
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and t1, v1, 0xfff8
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xor t1, t1, 0x9000 # 63-P1
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9008 # 63-P2
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beqz t1, 4f
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and t1, v1, 0xfff8
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xor t1, t1, 0x9100 # 68-P1
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beqz t1, 4f
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and t1, v1, 0xff00
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xor t1, t1, 0x9200 # 66-PX
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bnez t1, 5f # Skip WAR for others.
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and t1, v1, 0x00ff
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slti t1, t1, 2 # 66-P1.2 and later good.
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beqz t1, 5f
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4: # core-16057 work around
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or v0, v0, 0x2000 # Set IPREF bit.
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5: # No core-16057 work around
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# Write the cavium control register
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dmtc0 v0, CP0_CVMCTL_REG
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sync
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