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drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*
Prefer acronym-based naming to be in line with the rest of the driver. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220112111740.1208374-1-jani.nikula@intel.com
This commit is contained in:
parent
2616be2eac
commit
6650ebcbea
15 changed files with 70 additions and 102 deletions
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@ -75,10 +75,9 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
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u16 dclk;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
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&val, &val2);
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ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
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&val, &val2);
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if (ret)
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return ret;
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@ -102,10 +101,8 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
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int ret;
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int i;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ADL_PCODE_MEM_SS_READ_PSF_GV_INFO,
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&val, NULL);
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ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
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if (ret)
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return ret;
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@ -805,8 +805,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
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"trying to change cdclk frequency with cdclk not enabled\n"))
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return;
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ret = sandybridge_pcode_write(dev_priv,
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BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
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ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
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if (ret) {
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drm_err(&dev_priv->drm,
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"failed to inform pcode about cdclk change\n");
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@ -834,8 +833,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
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LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
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drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
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sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
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cdclk_config->voltage_level);
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snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
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cdclk_config->voltage_level);
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intel_de_write(dev_priv, CDCLK_FREQ,
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DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
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@ -1138,8 +1137,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
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intel_de_posting_read(dev_priv, CDCLK_CTL);
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/* inform PCU of the change */
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sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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cdclk_config->voltage_level);
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snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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cdclk_config->voltage_level);
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intel_update_cdclk(dev_priv);
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}
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@ -1717,10 +1716,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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* BSpec requires us to wait up to 150usec, but that leads to
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* timeouts; the 2ms used here is based on experiment.
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*/
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ret = sandybridge_pcode_write_timeout(dev_priv,
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HSW_PCODE_DE_WRITE_FREQ_REQ,
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0x80000000, 150, 2);
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ret = snb_pcode_write_timeout(dev_priv,
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HSW_PCODE_DE_WRITE_FREQ_REQ,
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0x80000000, 150, 2);
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if (ret) {
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drm_err(&dev_priv->drm,
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"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
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@ -1781,8 +1779,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
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if (DISPLAY_VER(dev_priv) >= 11) {
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ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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cdclk_config->voltage_level);
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ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
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cdclk_config->voltage_level);
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} else {
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/*
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* The timeout isn't specified, the 2ms used here is based on
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@ -1790,10 +1788,10 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
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* FIXME: Waiting for the request completion could be delayed
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* until the next PCODE request based on BSpec.
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*/
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ret = sandybridge_pcode_write_timeout(dev_priv,
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HSW_PCODE_DE_WRITE_FREQ_REQ,
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cdclk_config->voltage_level,
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150, 2);
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ret = snb_pcode_write_timeout(dev_priv,
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HSW_PCODE_DE_WRITE_FREQ_REQ,
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cdclk_config->voltage_level,
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150, 2);
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}
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if (ret) {
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@ -1118,8 +1118,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
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drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
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if (IS_BROADWELL(dev_priv)) {
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drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
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IPS_ENABLE | IPS_PCODE_CONTROL));
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drm_WARN_ON(dev, snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
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IPS_ENABLE | IPS_PCODE_CONTROL));
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/* Quoting Art Runyan: "its not safe to expect any particular
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* value in IPS_CTL bit 31 after enabling IPS through the
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* mailbox." Moreover, the mailbox may return a bogus state,
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@ -1149,7 +1149,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
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if (IS_BROADWELL(dev_priv)) {
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drm_WARN_ON(dev,
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sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
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snb_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
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/*
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* Wait for PCODE to finish disabling IPS. The BSpec specified
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* 42ms timeout value leads to occasional timeouts so use 100ms
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@ -683,9 +683,8 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
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int ret, tries = 0;
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while (1) {
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ret = sandybridge_pcode_write_timeout(i915,
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ICL_PCODE_EXIT_TCCOLD,
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0, 250, 1);
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ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
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250, 1);
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if (ret != -EAGAIN || ++tries == 3)
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break;
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msleep(1);
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@ -4053,8 +4052,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
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* Spec states that we should timeout the request after 200us
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* but the function below will timeout after 500us
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*/
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ret = sandybridge_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
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&high_val);
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ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
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if (ret == 0) {
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if (block &&
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(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
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@ -5469,8 +5467,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
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static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
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{
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if (IS_HASWELL(dev_priv)) {
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if (sandybridge_pcode_write(dev_priv,
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GEN6_PCODE_WRITE_D_COMP, val))
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if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
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drm_dbg_kms(&dev_priv->drm,
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"Failed to write to D_COMP\n");
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} else {
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@ -297,8 +297,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
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* Mailbox interface.
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*/
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if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
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ret = sandybridge_pcode_write(dev_priv,
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SKL_PCODE_LOAD_HDCP_KEYS, 1);
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ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
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if (ret) {
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drm_err(&dev_priv->drm,
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"Failed to initiate HDCP key load (%d)\n",
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@ -134,8 +134,7 @@ static int gen6_drpc(struct seq_file *m)
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}
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if (GRAPHICS_VER(i915) <= 7)
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sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
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&rc6vids, NULL);
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snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
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seq_printf(m, "RC1e Enabled: %s\n",
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yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
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@ -557,9 +556,8 @@ static int llc_show(struct seq_file *m, void *data)
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wakeref = intel_runtime_pm_get(gt->uncore->rpm);
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for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
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ia_freq = gpu_freq;
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sandybridge_pcode_read(i915,
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&ia_freq, NULL);
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snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&ia_freq, NULL);
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seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
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intel_gpu_freq(rps,
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(gpu_freq *
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@ -140,11 +140,10 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
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unsigned int ia_freq, ring_freq;
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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sandybridge_pcode_write(i915,
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GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
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ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
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ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
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gpu_freq);
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snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
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ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
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ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
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gpu_freq);
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}
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}
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@ -261,8 +261,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
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GEN6_RC_CTL_HW_ENABLE;
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rc6vids = 0;
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ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
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&rc6vids, NULL);
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ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
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if (GRAPHICS_VER(i915) == 6 && ret) {
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drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
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} else if (GRAPHICS_VER(i915) == 6 &&
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@ -272,7 +271,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
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GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
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rc6vids &= 0xffff00;
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rc6vids |= GEN6_ENCODE_RC6_VID(450);
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ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
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ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
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if (ret)
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drm_err(&i915->drm,
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"Couldn't fix incorrect rc6 voltage\n");
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@ -1019,9 +1019,8 @@ static void gen6_rps_init(struct intel_rps *rps)
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IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11) {
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u32 ddcc_status = 0;
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if (sandybridge_pcode_read(i915,
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HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
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&ddcc_status, NULL) == 0)
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if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
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&ddcc_status, NULL) == 0)
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rps->efficient_freq =
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clamp_t(u8,
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(ddcc_status >> 8) & 0xff,
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@ -1869,8 +1868,7 @@ void intel_rps_init(struct intel_rps *rps)
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if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
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u32 params = 0;
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sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
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¶ms, NULL);
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snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
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if (params & BIT(31)) { /* OC supported */
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drm_dbg(&i915->drm,
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"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
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@ -31,9 +31,8 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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val = gpu_freq;
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if (sandybridge_pcode_read(i915,
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&val, NULL)) {
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if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&val, NULL)) {
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pr_err("Failed to read freq table[%d], range [%d, %d]\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
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err = -ENXIO;
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@ -519,9 +519,8 @@ static void show_pcu_config(struct intel_rps *rps)
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for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
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int ia_freq = gpu_freq;
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sandybridge_pcode_read(i915,
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&ia_freq, NULL);
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snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&ia_freq, NULL);
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pr_info("%5d %5d %5d\n",
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gpu_freq * 50,
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@ -389,10 +389,8 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
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u32 val = 0;
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int ret;
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ret = sandybridge_pcode_read(dev_priv,
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ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_GLOBAL_INFO,
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&val, NULL);
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ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
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ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
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if (ret)
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return ret;
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@ -51,11 +51,10 @@ static int gen7_check_mailbox_status(u32 mbox)
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}
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}
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static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
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u32 mbox, u32 *val, u32 *val1,
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int fast_timeout_us,
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int slow_timeout_ms,
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bool is_read)
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static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
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u32 *val, u32 *val1,
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int fast_timeout_us, int slow_timeout_ms,
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bool is_read)
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{
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struct intel_uncore *uncore = &i915->uncore;
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@ -94,15 +93,12 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
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return gen6_check_mailbox_status(mbox);
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}
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int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
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u32 *val, u32 *val1)
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int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
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{
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int err;
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mutex_lock(&i915->sb_lock);
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err = __sandybridge_pcode_rw(i915, mbox, val, val1,
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500, 20,
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true);
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err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
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mutex_unlock(&i915->sb_lock);
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if (err) {
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@ -114,17 +110,14 @@ int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
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return err;
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}
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int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
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u32 mbox, u32 val,
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int fast_timeout_us,
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int slow_timeout_ms)
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int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
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int fast_timeout_us, int slow_timeout_ms)
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{
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int err;
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mutex_lock(&i915->sb_lock);
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err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
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fast_timeout_us, slow_timeout_ms,
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false);
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err = __snb_pcode_rw(i915, mbox, &val, NULL,
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fast_timeout_us, slow_timeout_ms, false);
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mutex_unlock(&i915->sb_lock);
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if (err) {
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@ -140,9 +133,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
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u32 request, u32 reply_mask, u32 reply,
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u32 *status)
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{
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*status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
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500, 0,
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true);
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*status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
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return *status || ((request & reply_mask) == reply);
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}
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@ -10,13 +10,11 @@
|
|||
|
||||
struct drm_i915_private;
|
||||
|
||||
int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
|
||||
u32 *val, u32 *val1);
|
||||
int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
|
||||
u32 val, int fast_timeout_us,
|
||||
int slow_timeout_ms);
|
||||
#define sandybridge_pcode_write(i915, mbox, val) \
|
||||
sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
|
||||
int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
|
||||
int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
|
||||
int fast_timeout_us, int slow_timeout_ms);
|
||||
#define snb_pcode_write(i915, mbox, val) \
|
||||
snb_pcode_write_timeout(i915, mbox, val, 500, 0)
|
||||
|
||||
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
|
||||
u32 reply_mask, u32 reply, int timeout_base_ms);
|
||||
|
|
|
@ -2890,9 +2890,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
|
|||
|
||||
/* read the first set of memory latencies[0:3] */
|
||||
val = 0; /* data0 to be programmed to 0 for first set */
|
||||
ret = sandybridge_pcode_read(dev_priv,
|
||||
GEN9_PCODE_READ_MEM_LATENCY,
|
||||
&val, NULL);
|
||||
ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
|
||||
&val, NULL);
|
||||
|
||||
if (ret) {
|
||||
drm_err(&dev_priv->drm,
|
||||
|
@ -2910,9 +2909,8 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
|
|||
|
||||
/* read the second set of memory latencies[4:7] */
|
||||
val = 1; /* data0 to be programmed to 1 for second set */
|
||||
ret = sandybridge_pcode_read(dev_priv,
|
||||
GEN9_PCODE_READ_MEM_LATENCY,
|
||||
&val, NULL);
|
||||
ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
|
||||
&val, NULL);
|
||||
if (ret) {
|
||||
drm_err(&dev_priv->drm,
|
||||
"SKL Mailbox read error = %d\n", ret);
|
||||
|
@ -3702,9 +3700,9 @@ skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
|
|||
u32 val = 0;
|
||||
int ret;
|
||||
|
||||
ret = sandybridge_pcode_read(dev_priv,
|
||||
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
|
||||
&val, NULL);
|
||||
ret = snb_pcode_read(dev_priv,
|
||||
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
|
||||
&val, NULL);
|
||||
if (!ret) {
|
||||
dev_priv->sagv_block_time_us = val;
|
||||
return;
|
||||
|
@ -3751,8 +3749,8 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
|
|||
return 0;
|
||||
|
||||
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
|
||||
ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
|
||||
GEN9_SAGV_ENABLE);
|
||||
ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
|
||||
GEN9_SAGV_ENABLE);
|
||||
|
||||
/* We don't need to wait for SAGV when enabling */
|
||||
|
||||
|
|
Loading…
Reference in a new issue