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irqchip/gic-v3: Don't try to reset AP0Rn
Clearing AP0Rn has created a number of regressions, due to systems
that have SCR_EL3.FIQ set. Even when addressing some obvious bugs,
GIC500 platforms seem to act bizarrely (we are supposed to have
5 bits of priority, but PMR seems to behave as if we had 6...).
Drop the AP0Rn reset for the time being, it is unlikely to have any
effect if kexec-ing.
Fixes: d6062a6d62
irqchip/gic-v3: Reset APgRn registers at boot time
Reported-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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1 changed files with 0 additions and 4 deletions
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@ -570,16 +570,12 @@ static void gic_cpu_sys_reg_init(void)
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switch(val + 1) {
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case 8:
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case 7:
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write_gicreg(0, ICC_AP0R3_EL1);
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write_gicreg(0, ICC_AP1R3_EL1);
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write_gicreg(0, ICC_AP0R2_EL1);
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write_gicreg(0, ICC_AP1R2_EL1);
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case 6:
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write_gicreg(0, ICC_AP0R1_EL1);
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write_gicreg(0, ICC_AP1R1_EL1);
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case 5:
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case 4:
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write_gicreg(0, ICC_AP0R0_EL1);
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write_gicreg(0, ICC_AP1R0_EL1);
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}
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