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perf_events, x86: Remove superflous MSR writes

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We re-program the event control register every time we reset the count,
this appears to be superflous, hence remove it.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arjan van de Ven <arjan@linux.intel.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra 2010-02-10 16:10:48 +01:00 committed by Ingo Molnar
parent 6e37738a2f
commit 6667661df4
1 changed files with 0 additions and 3 deletions
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3
arch/x86/kernel/cpu/perf_event.c
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@ -2009,9 +2009,6 @@ static int intel_pmu_save_and_restart(struct perf_event *event)
x86_perf_event_update(event, hwc, idx);
ret = x86_perf_event_set_period(event, hwc, idx);
if (event->state == PERF_EVENT_STATE_ACTIVE)
intel_pmu_enable_event(hwc, idx);
return ret;
}