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clk: JZ4780: Add function for enable the second core.
Add "jz4780_core1_enable()" for enable the second core of JZ4780, prepare for later commits. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1 changed files with 50 additions and 5 deletions
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@ -9,14 +9,16 @@
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/jz4780-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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/* CGU register offsets */
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#define CGU_REG_CLOCKCONTROL 0x00
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#define CGU_REG_PLLCONTROL 0x0c
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#define CGU_REG_LCR 0x04
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#define CGU_REG_APLL 0x10
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#define CGU_REG_MPLL 0x14
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#define CGU_REG_EPLL 0x18
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@ -46,8 +48,8 @@
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#define CGU_REG_CLOCKSTATUS 0xd4
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/* bits within the OPCR register */
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#define OPCR_SPENDN0 (1 << 7)
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#define OPCR_SPENDN1 (1 << 6)
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#define OPCR_SPENDN0 BIT(7)
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#define OPCR_SPENDN1 BIT(6)
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/* bits within the USBPCR register */
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#define USBPCR_USB_MODE BIT(31)
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@ -88,6 +90,13 @@
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#define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT)
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#define USBVBFIL_USBVBFIL_MASK (0xffff)
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/* bits within the LCR register */
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#define LCR_PD_SCPU BIT(31)
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#define LCR_SCPUS BIT(27)
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/* bits within the CLKGR1 register */
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#define CLKGR1_CORE1 BIT(15)
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static struct ingenic_cgu *cgu;
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static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
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@ -205,6 +214,42 @@ static const struct clk_ops jz4780_otg_phy_ops = {
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.set_rate = jz4780_otg_phy_set_rate,
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};
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static int jz4780_core1_enable(struct clk_hw *hw)
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{
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struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
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struct ingenic_cgu *cgu = ingenic_clk->cgu;
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const unsigned int timeout = 5000;
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unsigned long flags;
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int retval;
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u32 lcr, clkgr1;
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spin_lock_irqsave(&cgu->lock, flags);
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lcr = readl(cgu->base + CGU_REG_LCR);
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lcr &= ~LCR_PD_SCPU;
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writel(lcr, cgu->base + CGU_REG_LCR);
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clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
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clkgr1 &= ~CLKGR1_CORE1;
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writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
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spin_unlock_irqrestore(&cgu->lock, flags);
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/* wait for the CPU to be powered up */
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retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr,
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!(lcr & LCR_SCPUS), 10, timeout);
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if (retval == -ETIMEDOUT) {
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pr_err("%s: Wait for power up core1 timeout\n", __func__);
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return retval;
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}
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return 0;
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}
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static const struct clk_ops jz4780_core1_ops = {
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.enable = jz4780_core1_enable,
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};
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static const s8 pll_od_encoding[16] = {
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0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
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0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
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@ -699,9 +744,9 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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},
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[JZ4780_CLK_CORE1] = {
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"core1", CGU_CLK_GATE,
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"core1", CGU_CLK_CUSTOM,
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.parents = { JZ4780_CLK_CPU, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR1, 15 },
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.custom = { &jz4780_core1_ops },
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},
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};
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