mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-30 08:02:30 +00:00
Code Issues Releases Wiki Activity

staging: rtl8192e: Remove dead code

Browse source 
Delete unused code. Removed some macros, enums, unions and several
structures (tx_fwinfo, wmm_tspec, qos_tstream, sta_qos, bss_qos).

Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mateusz Kulikowski 2015-06-02 22:48:05 +02:00 committed by Greg Kroah-Hartman
parent c1ab2fa969
commit 669adbe6c9
6 changed files with 0 additions and 250 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

40
drivers/staging/rtl8192e/rtl8192e/r8190P_def.h
View file

@ -144,19 +144,6 @@ enum rf_optype {
RF_OP_MAX
};
enum power_save_mode {
POWER_SAVE_MODE_ACTIVE,
POWER_SAVE_MODE_SAVE,
};
enum interface_select_8190pci {
INTF_SEL1_MINICARD = 0,
INTF_SEL0_PCIE = 1,
INTF_SEL2_RSV = 2,
INTF_SEL3_RSV = 3,
};
struct bb_reg_definition {
u32 rfintfs;
u32 rfintfi;
@ -178,33 +165,6 @@ struct bb_reg_definition {
u32 rfLSSIReadBackPi;
};
struct tx_fwinfo {
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
u8 RtsEnable:1;
u8 TxHT:1;
u8 Short:1;
u8 TxBandwidth:1;
u8 TxSubCarrier:2;
u8 STBC:2;
u8 AllowAggregation:1;
u8 RtsHT:1;
u8 RtsShort:1;
u8 RtsBandwidth:1;
u8 RtsSubcarrier:2;
u8 RtsSTBC:2;
u8 EnableCPUDur:1;
u32 RxMF:2;
u32 RxAMD:3;
u32 Reserved1:3;
u32 TxAGCOffset:4;
u32 TxAGCSign:1;
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
};
struct tx_fwinfo_8190pci {
u8 TxRate:7;
u8 CtsEnable:1;

5
drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.h
View file

@ -52,11 +52,6 @@ enum firmware_status {
FW_STATUS_5_READY = 5,
};
struct fw_seg_container {
u16 seg_size;
u8 *seg_ptr;
};
struct rt_firmware {
enum firmware_status firmware_status;
u16 cmdpacket_frag_thresold;

6
drivers/staging/rtl8192e/rtl8192e/r8192E_hwimg.h
View file

@ -23,12 +23,6 @@
#include <linux/types.h>
#define BootArrayLengthPciE 344
extern u8 Rtl8192PciEFwBootArray[BootArrayLengthPciE];
#define MainArrayLengthPciE 43012
extern u8 Rtl8192PciEFwMainArray[MainArrayLengthPciE];
#define DataArrayLengthPciE 848
extern u8 Rtl8192PciEFwDataArray[DataArrayLengthPciE];
#define PHY_REGArrayLengthPciE 1
extern u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE];
#define PHY_REG_1T2RArrayLengthPciE 296

1
drivers/staging/rtl8192e/rtl8192e/rtl_cam.h
View file

@ -34,7 +34,6 @@ void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType,
const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
void set_swcam(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType,
const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent, u8 is_mesh);
void CamPrintDbgReg(struct net_device *dev);
u32 read_cam(struct net_device *dev, u8 addr);
void write_cam(struct net_device *dev, u8 addr, u32 data);

4
drivers/staging/rtl8192e/rtl8192e/rtl_wx.h
View file

@ -20,11 +20,7 @@
#ifndef R819x_WX_H
#define R819x_WX_H
struct net_device;
struct iw_handler_def;
struct iw_statistics;
extern const struct iw_handler_def r8192_wx_handlers_def;
u16 rtl8192_11n_user_show_rates(struct net_device *dev);
#endif

194
drivers/staging/rtl8192e/rtl819x_Qos.h
View file

@ -91,122 +91,22 @@ union tspec_body {
} f;
};
struct wmm_tspec {
u8 ID;
u8 Length;
u8 OUI[3];
u8 OUI_Type;
u8 OUI_SubType;
u8 Version;
union tspec_body Body;
};
struct octet_string {
u8 *Octet;
u16 Length;
};
#define MAX_WMMELE_LENGTH 64
#define QOS_MODE u32
#define QOS_DISABLE 0
#define QOS_WMM 1
#define QOS_WMMSA 2
#define QOS_EDCA 4
#define QOS_HCCA 8
#define QOS_WMM_UAPSD 16
#define WMM_PARAM_ELE_BODY_LEN 18
#define MAX_STA_TS_COUNT 16
#define MAX_AP_TS_COUNT 32
#define QOS_TSTREAM_KEY_SIZE 13
#define WMM_ACTION_CATEGORY_CODE 17
#define WMM_PARAM_ELE_BODY_LEN 18
#define MAX_TSPEC_TSID 15
#define SESSION_REJECT_TSID 0xfe
#define DEFAULT_TSID 0xff
#define ADDTS_TIME_SLOT 100
#define ACM_TIMEOUT 1000
#define SESSION_REJECT_TIMEOUT 60000
enum ack_policy {
eAckPlc0_ACK = 0x00,
eAckPlc1_NoACK = 0x01,
};
#define SET_WMM_QOS_INFO_FIELD(_pStart, _val) \
WriteEF1Byte(_pStart, _val)
#define GET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 0, 4)
#define SET_WMM_QOS_INFO_FIELD_PARAMETERSET_COUNT(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 0, 4, _val)
#define GET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 7, 1)
#define SET_WMM_QOS_INFO_FIELD_AP_UAPSD(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 7, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 0, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_VO_UAPSD(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 0, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 1, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_VI_UAPSD(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 1, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 2, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_BE_UAPSD(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 2, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 3, 1)
#define SET_WMM_QOS_INFO_FIELD_STA_AC_BK_UAPSD(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 3, 1, _val)
#define GET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart) \
LE_BITS_TO_1BYTE(_pStart, 5, 2)
#define SET_WMM_QOS_INFO_FIELD_STA_MAX_SP_LEN(_pStart, _val) \
SET_BITS_TO_LE_1BYTE(_pStart, 5, 2, _val)
enum qos_ie_source {
QOSIE_SRC_ADDTSREQ,
QOSIE_SRC_ADDTSRSP,
QOSIE_SRC_REASOCREQ,
QOSIE_SRC_REASOCRSP,
QOSIE_SRC_DELTS,
};
#define AC_CODING u32
#define AC0_BE 0
#define AC1_BK 1
#define AC2_VI 2
#define AC3_VO 3
#define AC_MAX 4
#define AC_PARAM_SIZE 4
#define WMM_PARAM_ELEMENT_SIZE (8+(4*AC_PARAM_SIZE))
enum qos_ele_subtype {
QOSELE_TYPE_INFO = 0x00,
QOSELE_TYPE_PARAM = 0x01,
};
enum direction_value {
DIR_UP = 0,
DIR_DOWN = 1,
@ -227,22 +127,6 @@ struct acm {
u8 HwAcmCtl;
};
#define AC_UAPSD u8
#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2)
#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2)
#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3)
#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
union qos_tclas {
struct _TYPE_GENERAL {
@ -294,65 +178,6 @@ union qos_tclas {
} TYPE2_8021Q;
};
struct qos_tstream {
bool bUsed;
u16 MsduLifetime;
bool bEstablishing;
u8 TimeSlotCount;
u8 DialogToken;
struct wmm_tspec TSpec;
struct wmm_tspec OutStandingTSpec;
u8 NominalPhyRate;
};
struct sta_qos {
u8 WMMIEBuf[MAX_WMMELE_LENGTH];
u8 *WMMIE;
QOS_MODE QosCapability;
QOS_MODE CurrentQosMode;
AC_UAPSD b4ac_Uapsd;
AC_UAPSD Curr4acUapsd;
u8 bInServicePeriod;
u8 MaxSPLength;
int NumBcnBeforeTrigger;
u8 *pWMMInfoEle;
u8 WMMParamEle[WMM_PARAM_ELEMENT_SIZE];
struct acm acm[4];
enum acm_method AcmMethod;
struct qos_tstream StaTsArray[MAX_STA_TS_COUNT];
u8 DialogToken;
struct wmm_tspec TSpec;
u8 QBssWirelessMode;
bool bNoAck;
bool bEnableRxImmBA;
};
#define QBSS_LOAD_SIZE 5
struct bss_qos {
QOS_MODE bdQoSMode;
u8 bdWMMIEBuf[MAX_WMMELE_LENGTH];
struct octet_string bdWMMIE;
enum qos_ele_subtype EleSubType;
u8 *pWMMInfoEle;
u8 *pWMMParamEle;
u8 QBssLoad[QBSS_LOAD_SIZE];
bool bQBssLoadValid;
};
#define IsACValid(ac) ((ac >= 0 && ac <= 7) ? true : false)
@ -367,23 +192,4 @@ union aci_aifsn {
} f;
};
union ecw {
u8 charData;
struct {
u8 ECWmin:4;
u8 ECWmax:4;
} f;
};
union ac_param {
u32 longData;
u8 charData[4];
struct {
union aci_aifsn AciAifsn;
union ecw Ecw;
u16 TXOPLimit;
} f;
};
#endif