RISC-V DeviceTrees for v6.2
dt-bindings: - new compatibles to support the StarFive VisionFive & thead CPU cores - a fix for the PolarFire SoC's pwm binding, merged through my tree as suggested by the PWM maintainers Microchip: - Non-urgent fix for the node address not matches the reg in a way that the checkers don't complain about - Add GPIO controlled LEDs for Icicle - Support for the "CCC" clocks in the FPGA fabric. Previously these used fixed-frequency clocks in the dt, but if which CCC is in use is known, as in the v2022.09 Icicle Kit Reference Design, the rates can be read dynamically. It's an "is known" as it *can* be set via constraints in the FPGA tooling but does not have to be. - A fix for the Icicle's pwm-cells - Removal of some unused PCI clocks StarFive: - Addition of the VisionFive DT, which has been a long time coming! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY3tLkQAKCRB4tDGHoIJi 0qM+AP9i7GnanM9SfzeRaftL/JO2RrDcM0QGW9tkE0DVsVyzugD+OxkxV4LJS9GJ O4UBM7APtCNJ7hUvvCQpikdAT2POKAI= =37HZ -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V DeviceTrees for v6.2 dt-bindings: - new compatibles to support the StarFive VisionFive & thead CPU cores - a fix for the PolarFire SoC's pwm binding, merged through my tree as suggested by the PWM maintainers Microchip: - Non-urgent fix for the node address not matches the reg in a way that the checkers don't complain about - Add GPIO controlled LEDs for Icicle - Support for the "CCC" clocks in the FPGA fabric. Previously these used fixed-frequency clocks in the dt, but if which CCC is in use is known, as in the v2022.09 Icicle Kit Reference Design, the rates can be read dynamically. It's an "is known" as it *can* be set via constraints in the FPGA tooling but does not have to be. - A fix for the Icicle's pwm-cells - Removal of some unused PCI clocks StarFive: - Addition of the VisionFive DT, which has been a long time coming! Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles riscv: dts: microchip: remove unused pcie clocks riscv: dts: microchip: remove pcie node from the sev kit riscv: dts: microchip: fix the icicle's #pwm-cells dt-bindings: pwm: fix microchip corePWM's pwm-cells riscv: dts: starfive: Add StarFive VisionFive V1 device tree riscv: dts: starfive: Add common DT for JH7100 based boards dt-bindings: riscv: starfive: Add StarFive VisionFive V1 board riscv: dts: microchip: fix memory node unit address for icicle riscv: dts: microchip: icicle: Add GPIO controlled LEDs riscv: dts: microchip: add the mpfs' fabric clock control Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
6721cf8585
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|
@ -30,7 +30,9 @@ properties:
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|||
maxItems: 1
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||||
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"#pwm-cells":
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const: 2
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enum: [2, 3]
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description:
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The only flag supported by the controller is PWM_POLARITY_INVERTED.
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microchip,sync-update-mask:
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description: |
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|
|
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@ -40,6 +40,8 @@ properties:
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- sifive,u7
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- sifive,u74
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- sifive,u74-mc
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- thead,c906
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- thead,c910
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- const: riscv
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- items:
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- enum:
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|
|
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@ -19,7 +19,9 @@ properties:
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compatible:
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oneOf:
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- items:
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- const: beagle,beaglev-starlight-jh7100-r0
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- enum:
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- beagle,beaglev-starlight-jh7100-r0
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- starfive,visionfive-v1
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- const: starfive,jh7100
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additionalProperties: true
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@ -9,8 +9,8 @@
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compatible = "microchip,corepwm-rtl-v4";
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reg = <0x0 0x40000000 0x0 0xF0>;
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microchip,sync-update-mask = /bits/ 32 <0>;
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#pwm-cells = <2>;
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clocks = <&fabric_clk3>;
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#pwm-cells = <3>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
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status = "disabled";
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};
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@ -19,25 +19,13 @@
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reg = <0x0 0x40000200 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&fabric_clk3>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
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interrupt-parent = <&plic>;
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interrupts = <122>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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fabric_clk3: fabric-clk3 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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fabric_clk1: fabric-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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pcie: pcie@3000000000 {
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compatible = "microchip,pcie-host-1.0";
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#address-cells = <0x3>;
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@ -54,7 +42,7 @@
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&fabric_clk1>, <&fabric_clk3>;
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clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
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clock-names = "fic1", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
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dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
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@ -67,4 +55,17 @@
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interrupt-controller;
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};
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};
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refclk_ccc: cccrefclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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&ccc_nw {
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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status = "okay";
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};
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@ -5,6 +5,8 @@
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#include "mpfs.dtsi"
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#include "mpfs-icicle-kit-fabric.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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@ -31,13 +33,41 @@
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timebase-frequency = <RTCCLK_FREQ>;
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};
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leds {
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compatible = "gpio-leds";
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led-1 {
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gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led1";
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};
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led-2 {
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gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_RED>;
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label = "led2";
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};
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led-3 {
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gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led3";
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};
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led-4 {
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gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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color = <LED_COLOR_ID_AMBER>;
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label = "led4";
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};
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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status = "okay";
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};
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ddrc_cache_hi: memory@1000000000 {
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ddrc_cache_hi: memory@1040000000 {
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device_type = "memory";
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reg = <0x10 0x40000000 0x0 0x40000000>;
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status = "okay";
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@ -149,6 +179,10 @@
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clock-frequency = <125000000>;
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};
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&refclk_ccc {
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clock-frequency = <50000000>;
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};
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&rtc {
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status = "okay";
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};
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@ -30,8 +30,8 @@
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic1", "fic3";
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clocks = <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
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msi-parent = <&pcie>;
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msi-controller;
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|
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@ -30,8 +30,8 @@
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic1", "fic3";
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clocks = <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
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msi-parent = <&pcie>;
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msi-controller;
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@ -13,33 +13,4 @@
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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pcie: pcie@2000000000 {
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compatible = "microchip,pcie-host-1.0";
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#address-cells = <0x3>;
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#interrupt-cells = <0x1>;
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#size-cells = <0x2>;
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device_type = "pci";
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reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
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reg-names = "cfg", "apb";
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bus-range = <0x0 0x7f>;
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interrupt-parent = <&plic>;
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interrupts = <119>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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interrupt-map-mask = <0 0 0 7>;
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clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
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clock-names = "fic0", "fic1", "fic3";
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ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
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msi-parent = <&pcie>;
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msi-controller;
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status = "disabled";
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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@ -236,6 +236,38 @@
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#clock-cells = <1>;
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};
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ccc_se: clock-controller@38010000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
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<0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_ne: clock-controller@38040000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
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<0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_nw: clock-controller@38100000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
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<0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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ccc_sw: clock-controller@38400000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
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<0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
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#clock-cells = <1>;
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status = "disabled";
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};
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mmuart0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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|
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@ -1,2 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
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dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
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|
|
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@ -5,160 +5,9 @@
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*/
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/dts-v1/;
|
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#include "jh7100.dtsi"
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#include <dt-bindings/gpio/gpio.h>
|
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#include <dt-bindings/leds/common.h>
|
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#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
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#include "jh7100-common.dtsi"
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|
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/ {
|
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model = "BeagleV Starlight Beta";
|
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compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
timebase-frequency = <6250000>;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x2 0x0>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-ack {
|
||||
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
linux,default-trigger = "heartbeat";
|
||||
label = "ack";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2c0_pins: i2c0-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(62, GPO_LOW,
|
||||
GPO_I2C0_PAD_SCK_OEN,
|
||||
GPI_I2C0_PAD_SCK_IN)>,
|
||||
<GPIOMUX(61, GPO_LOW,
|
||||
GPO_I2C0_PAD_SDA_OEN,
|
||||
GPI_I2C0_PAD_SDA_IN)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(47, GPO_LOW,
|
||||
GPO_I2C1_PAD_SCK_OEN,
|
||||
GPI_I2C1_PAD_SCK_IN)>,
|
||||
<GPIOMUX(48, GPO_LOW,
|
||||
GPO_I2C1_PAD_SDA_OEN,
|
||||
GPI_I2C1_PAD_SDA_IN)>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(60, GPO_LOW,
|
||||
GPO_I2C2_PAD_SCK_OEN,
|
||||
GPI_I2C2_PAD_SCK_IN)>,
|
||||
<GPIOMUX(59, GPO_LOW,
|
||||
GPO_I2C2_PAD_SDA_OEN,
|
||||
GPI_I2C2_PAD_SDA_IN)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart3_pins: uart3-0 {
|
||||
rx-pins {
|
||||
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
|
||||
GPI_UART3_PAD_SIN)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
tx-pins {
|
||||
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
|
||||
GPO_ENABLE, GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <35>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@5e {
|
||||
compatible = "ti,tps65086";
|
||||
reg = <0x5e>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
regulators {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&osc_sys {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&osc_aud {
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2021 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7100.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
timebase-frequency = <6250000>;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x2 0x0>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-ack {
|
||||
gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
linux,default-trigger = "heartbeat";
|
||||
label = "ack";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
i2c0_pins: i2c0-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(62, GPO_LOW,
|
||||
GPO_I2C0_PAD_SCK_OEN,
|
||||
GPI_I2C0_PAD_SCK_IN)>,
|
||||
<GPIOMUX(61, GPO_LOW,
|
||||
GPO_I2C0_PAD_SDA_OEN,
|
||||
GPI_I2C0_PAD_SDA_IN)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(47, GPO_LOW,
|
||||
GPO_I2C1_PAD_SCK_OEN,
|
||||
GPI_I2C1_PAD_SCK_IN)>,
|
||||
<GPIOMUX(48, GPO_LOW,
|
||||
GPO_I2C1_PAD_SDA_OEN,
|
||||
GPI_I2C1_PAD_SDA_IN)>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(60, GPO_LOW,
|
||||
GPO_I2C2_PAD_SCK_OEN,
|
||||
GPI_I2C2_PAD_SCK_IN)>,
|
||||
<GPIOMUX(59, GPO_LOW,
|
||||
GPO_I2C2_PAD_SDA_OEN,
|
||||
GPI_I2C2_PAD_SDA_IN)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart3_pins: uart3-0 {
|
||||
rx-pins {
|
||||
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
|
||||
GPI_UART3_PAD_SIN)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
tx-pins {
|
||||
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
|
||||
GPO_ENABLE, GPI_NONE)>;
|
||||
bias-disable;
|
||||
drive-strength = <35>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
|
||||
pmic@5e {
|
||||
compatible = "ti,tps65086";
|
||||
reg = <0x5e>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
regulators {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <500>;
|
||||
i2c-scl-falling-time-ns = <500>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&osc_sys {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&osc_aud {
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2021 StarFive Technology Co., Ltd.
|
||||
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "jh7100-common.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "StarFive VisionFive V1";
|
||||
compatible = "starfive,visionfive-v1", "starfive,jh7100";
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
|
||||
priority = <224>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue