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drm/amdgpu: cleanup UAPI comments
No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
692a59e696
commit
675da0ddd6
1 changed files with 79 additions and 42 deletions
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@ -141,12 +141,17 @@ union drm_amdgpu_bo_list {
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/* GPU reset status */
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#define AMDGPU_CTX_NO_RESET 0
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#define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */
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#define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */
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#define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */
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/* this the context caused it */
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#define AMDGPU_CTX_GUILTY_RESET 1
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/* some other context caused it */
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#define AMDGPU_CTX_INNOCENT_RESET 2
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/* unknown cause */
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#define AMDGPU_CTX_UNKNOWN_RESET 3
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struct drm_amdgpu_ctx_in {
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/** AMDGPU_CTX_OP_* */
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uint32_t op;
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/** For future use, no flags defined so far */
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uint32_t flags;
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uint32_t ctx_id;
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uint32_t _pad;
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@ -159,6 +164,7 @@ union drm_amdgpu_ctx_out {
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} alloc;
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struct {
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/** For future use, no flags defined so far */
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uint64_t flags;
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/** Number of resets caused by this context so far. */
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uint32_t hangs;
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@ -185,7 +191,9 @@ union drm_amdgpu_ctx {
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struct drm_amdgpu_gem_userptr {
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uint64_t addr;
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uint64_t size;
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/* AMDGPU_GEM_USERPTR_* */
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uint32_t flags;
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/* Resulting GEM handle */
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uint32_t handle;
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};
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@ -217,23 +225,29 @@ struct drm_amdgpu_gem_userptr {
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/** The same structure is shared for input/output */
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struct drm_amdgpu_gem_metadata {
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uint32_t handle; /* GEM Object handle */
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uint32_t op; /** Do we want get or set metadata */
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/** GEM Object handle */
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uint32_t handle;
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/** Do we want get or set metadata */
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uint32_t op;
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struct {
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/** For future use, no flags defined so far */
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uint64_t flags;
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uint64_t tiling_info; /* family specific tiling info */
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/** family specific tiling info */
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uint64_t tiling_info;
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uint32_t data_size_bytes;
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uint32_t data[64];
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} data;
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};
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struct drm_amdgpu_gem_mmap_in {
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uint32_t handle; /** the GEM object handle */
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/** the GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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};
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struct drm_amdgpu_gem_mmap_out {
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uint64_t addr_ptr; /** mmap offset from the vma offset manager */
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/** mmap offset from the vma offset manager */
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uint64_t addr_ptr;
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};
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union drm_amdgpu_gem_mmap {
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@ -242,14 +256,19 @@ union drm_amdgpu_gem_mmap {
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};
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struct drm_amdgpu_gem_wait_idle_in {
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uint32_t handle; /* GEM object handle */
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/** GEM object handle */
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uint32_t handle;
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/** For future use, no flags defined so far */
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uint32_t flags;
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uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */
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/** Absolute timeout to wait */
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uint64_t timeout;
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};
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struct drm_amdgpu_gem_wait_idle_out {
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uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */
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uint32_t domain; /* Returned current memory domain */
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/** BO status: 0 - BO is idle, 1 - BO is busy */
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uint32_t status;
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/** Returned current memory domain */
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uint32_t domain;
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};
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union drm_amdgpu_gem_wait_idle {
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@ -258,7 +277,9 @@ union drm_amdgpu_gem_wait_idle {
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};
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struct drm_amdgpu_wait_cs_in {
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/** Command submission handle */
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uint64_t handle;
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/** Absolute timeout to wait */
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uint64_t timeout;
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uint32_t ip_type;
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uint32_t ip_instance;
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@ -267,6 +288,7 @@ struct drm_amdgpu_wait_cs_in {
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};
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struct drm_amdgpu_wait_cs_out {
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/** CS status: 0 - CS completed, 1 - CS still busy */
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uint64_t status;
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};
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@ -275,16 +297,19 @@ union drm_amdgpu_wait_cs {
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struct drm_amdgpu_wait_cs_out out;
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};
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/* Sets or returns a value associated with a buffer. */
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struct drm_amdgpu_gem_op {
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uint32_t handle; /* buffer */
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uint32_t op; /* AMDGPU_GEM_OP_* */
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uint64_t value; /* input or return value */
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};
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#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
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#define AMDGPU_GEM_OP_SET_PLACEMENT 1
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/* Sets or returns a value associated with a buffer. */
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struct drm_amdgpu_gem_op {
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/** GEM object handle */
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uint32_t handle;
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/** AMDGPU_GEM_OP_* */
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uint32_t op;
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/** Input or return value */
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uint64_t value;
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};
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#define AMDGPU_VA_OP_MAP 1
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#define AMDGPU_VA_OP_UNMAP 2
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@ -297,19 +322,18 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
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struct drm_amdgpu_gem_va {
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/* GEM object handle */
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/** GEM object handle */
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uint32_t handle;
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uint32_t _pad;
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/* map or unmap*/
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/** AMDGPU_VA_OP_* */
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uint32_t operation;
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/* specify mapping flags */
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/** AMDGPU_VM_PAGE_* */
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uint32_t flags;
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/* va address to assign . Must be correctly aligned.*/
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/** va address to assign . Must be correctly aligned.*/
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uint64_t va_address;
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/* Specify offset inside of BO to assign. Must be correctly aligned.*/
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/** Specify offset inside of BO to assign. Must be correctly aligned.*/
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uint64_t offset_in_bo;
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/* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/
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/* Must be correctly aligned. */
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/** Specify mapping size. Must be correctly aligned. */
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uint64_t map_size;
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};
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@ -324,6 +348,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_IB 0x01
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#define AMDGPU_CHUNK_ID_FENCE 0x02
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struct drm_amdgpu_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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@ -337,7 +362,7 @@ struct drm_amdgpu_cs_in {
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uint32_t bo_list_handle;
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uint32_t num_chunks;
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uint32_t _pad;
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/* this points to uint64_t * which point to cs chunks */
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/** this points to uint64_t * which point to cs chunks */
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uint64_t chunks;
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};
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@ -346,8 +371,8 @@ struct drm_amdgpu_cs_out {
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};
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union drm_amdgpu_cs {
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struct drm_amdgpu_cs_in in;
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struct drm_amdgpu_cs_out out;
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struct drm_amdgpu_cs_in in;
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struct drm_amdgpu_cs_out out;
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};
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/* Specify flags to be used for IB */
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@ -360,12 +385,18 @@ union drm_amdgpu_cs {
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struct drm_amdgpu_cs_chunk_ib {
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uint32_t _pad;
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uint32_t flags; /* IB Flags */
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uint64_t va_start; /* Virtual address to begin IB execution */
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uint32_t ib_bytes; /* Size of submission */
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uint32_t ip_type; /* HW IP to submit to */
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uint32_t ip_instance; /* HW IP index of the same type to submit to */
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uint32_t ring; /* Ring index to submit to */
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/** AMDGPU_IB_FLAG_* */
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uint32_t flags;
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/** Virtual address to begin IB execution */
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uint64_t va_start;
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/** Size of submission */
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uint32_t ib_bytes;
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/** HW IP to submit to */
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uint32_t ip_type;
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/** HW IP index of the same type to submit to */
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uint32_t ip_instance;
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/** Ring index to submit to */
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uint32_t ring;
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};
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struct drm_amdgpu_cs_chunk_fence {
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@ -460,23 +491,28 @@ struct drm_amdgpu_info {
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/** AMDGPU_HW_IP_* */
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uint32_t type;
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/**
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* Index of the IP if there are more IPs of the same type.
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* Ignored by AMDGPU_INFO_HW_IP_COUNT.
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* Index of the IP if there are more IPs of the same
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* type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
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*/
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uint32_t ip_instance;
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} query_hw_ip;
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struct {
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uint32_t dword_offset;
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uint32_t count; /* number of registers to read */
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/** number of registers to read */
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uint32_t count;
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uint32_t instance;
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/** For future use, no flags defined so far */
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uint32_t flags;
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} read_mmr_reg;
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struct {
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/** AMDGPU_INFO_FW_* */
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uint32_t fw_type;
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/** Index of the IP if there are more IPs of the same type. */
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/**
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* Index of the IP if there are more IPs of
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* the same type.
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*/
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uint32_t ip_instance;
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/**
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* Index of the engine. Whether this is used depends
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@ -537,9 +573,10 @@ struct drm_amdgpu_info_device {
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uint32_t family;
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uint32_t num_shader_engines;
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uint32_t num_shader_arrays_per_engine;
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uint32_t gpu_counter_freq; /* in KHz */
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uint64_t max_engine_clock; /* in KHz */
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uint64_t max_memory_clock; /* in KHz */
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/* in KHz */
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uint32_t gpu_counter_freq;
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uint64_t max_engine_clock;
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uint64_t max_memory_clock;
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/* cu information */
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uint32_t cu_active_number;
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uint32_t cu_ao_mask;
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