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ARM: 6272/1: Convert L2x0 to use the IO relaxed operations
This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Since the mandatory barriers may do an L2 cache sync, this patch avoids a recursive call into l2x0_cache_sync() via the write*() accessors and wmb() and a call into l2x0_cache_sync() with the l2x0_lock held. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
e936771a76
commit
6775a558fe
1 changed files with 13 additions and 13 deletions
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@ -32,14 +32,14 @@ static uint32_t l2x0_way_mask; /* Bitmask of active ways */
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* wait for the operation to complete */
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while (readl(reg) & mask)
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while (readl_relaxed(reg) & mask)
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;
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}
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static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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writel(0, base + L2X0_CACHE_SYNC);
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writel_relaxed(0, base + L2X0_CACHE_SYNC);
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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@ -47,14 +47,14 @@ static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#ifdef CONFIG_PL310_ERRATA_588369
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@ -75,9 +75,9 @@ static inline void l2x0_flush_line(unsigned long addr)
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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writel_relaxed(addr, base + L2X0_INV_LINE_PA);
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}
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#else
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@ -90,7 +90,7 @@ static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
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writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
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}
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#endif
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@ -109,7 +109,7 @@ static inline void l2x0_inv_all(void)
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/* invalidate all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
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cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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@ -215,8 +215,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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l2x0_base = base;
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cache_id = readl(l2x0_base + L2X0_CACHE_ID);
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aux = readl(l2x0_base + L2X0_AUX_CTRL);
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cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
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aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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@ -248,15 +248,15 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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* If you are booting from non-secure mode
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* accessing the below registers will fault.
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*/
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if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
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if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) {
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/* l2x0 controller is disabled */
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writel(aux, l2x0_base + L2X0_AUX_CTRL);
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writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel(1, l2x0_base + L2X0_CTRL);
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writel_relaxed(1, l2x0_base + L2X0_CTRL);
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}
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outer_cache.inv_range = l2x0_inv_range;
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