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Three fixes, one for the clk framework and two for clk drivers:
- Avoid an oops in possible_parent_show() by checking for no parent properly when a DT index based lookup is used - Handle errors returned from divider_ro_round_rate() in clk_stm32_composite_determine_rate() - Fix clk_ops::determine_rate() implementation of socfpga's gateclk_ops that was ruining uart output because the divider was forgotten about -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmU8aqARHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSV9Ew/+LbRC35Dp9liQnF/kpggdfvr1QKDP+bWz m6Kp9+ZQ6xWcVDV+0Fjbrs/0+QB5R8PS9U/GIQTGcMce0QJwoOnK2eWf22h1H59i h6nHAUBuDURAotPOIITKn/1McLkznvW+6XUOJ/yBFCsjlqspYlnR222RXOqZrhH1 k/p1LE0dCXeiR07oJSoCsfVA5+ZzoFMRhpijoqjqOwMraMcX34CY3adOdM0WDvvH j10+9L0Bg5I/Y2NrP5ZfO2zmVVDFRrXuEfB6FlB54o9UDFLydCv6M96S1G4jmFcE s51mhoVhnxM+DG2Z9DNivPM5e8s1Q3yzvZko045kl86PqNwPw+LiezXwPSGcckKq 5eD6+08yKXgDlHzvCj5/hXO3X/1+HthdxCXXim4/oe+1PYn0tm3gYbyJ/RNMbHRP x7fYslZXB0rIOV5owO2UfYWqZ3SGpxe+WHdEOnfxyePmx4tVPEccNGDyV4BFBDBE hUrDrnoJBT6rKFYyvt7V0s5y11tdNOA0/TrzkZuwXNPDWeBLGGpEm0iHcBakrGjP TWHgFYYdABxwIgcB6aMvzfj1n3vETQKWpCd0nBI73RKz+ZP9ZmVTThSe17yCSjoj PhozYiv09gZ0ZfJWj6WHj/roJKErkM+Vk+9aC6dM8N3/CyJ5GofXUSf9lrquqBoy /BFyI4siNO4= =Hghf -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "Three fixes, one for the clk framework and two for clk drivers: - Avoid an oops in possible_parent_show() by checking for no parent properly when a DT index based lookup is used - Handle errors returned from divider_ro_round_rate() in clk_stm32_composite_determine_rate() - Fix clk_ops::determine_rate() implementation of socfpga's gateclk_ops that was ruining uart output because the divider was forgotten about" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate() clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name clk: socfpga: gate: Account for the divider in determine_rate
This commit is contained in:
commit
67d4c87945
3 changed files with 36 additions and 14 deletions
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@ -3416,6 +3416,7 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
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unsigned int i, char terminator)
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{
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struct clk_core *parent;
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const char *name = NULL;
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/*
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* Go through the following options to fetch a parent's name.
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@ -3430,18 +3431,20 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
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* registered (yet).
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*/
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parent = clk_core_get_parent_by_index(core, i);
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if (parent)
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if (parent) {
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seq_puts(s, parent->name);
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else if (core->parents[i].name)
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} else if (core->parents[i].name) {
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seq_puts(s, core->parents[i].name);
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else if (core->parents[i].fw_name)
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} else if (core->parents[i].fw_name) {
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seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
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else if (core->parents[i].index >= 0)
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seq_puts(s,
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of_clk_get_parent_name(core->of_node,
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core->parents[i].index));
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else
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seq_puts(s, "(missing)");
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} else {
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if (core->parents[i].index >= 0)
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name = of_clk_get_parent_name(core->of_node, core->parents[i].index);
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if (!name)
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name = "(missing)";
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seq_puts(s, name);
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}
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seq_putc(s, terminator);
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}
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@ -87,10 +87,8 @@ static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
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return 0;
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}
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static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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static u32 socfpga_clk_get_div(struct socfpga_gate_clk *socfpgaclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div)
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@ -105,12 +103,33 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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div = (1 << val);
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}
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return div;
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}
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static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = socfpga_clk_get_div(socfpgaclk);
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return parent_rate / div;
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}
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static int socfpga_clk_determine_rate(struct clk_hw *hwclk,
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struct clk_rate_request *req)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = socfpga_clk_get_div(socfpgaclk);
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req->rate = req->best_parent_rate / div;
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return 0;
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}
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static struct clk_ops gateclk_ops = {
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.recalc_rate = socfpga_clk_recalc_rate,
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.determine_rate = clk_hw_determine_rate_no_reparent,
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.determine_rate = socfpga_clk_determine_rate,
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.get_parent = socfpga_clk_get_parent,
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.set_parent = socfpga_clk_set_parent,
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};
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@ -431,7 +431,7 @@ static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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const struct stm32_div_cfg *divider;
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unsigned long rate;
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long rate;
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if (composite->div_id == NO_STM32_DIV)
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return 0;
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