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i2c: mlxbf: Update reference clock frequency
The reference clock frequency remains the same across Bluefield
products. Thus, update the frequency and rename the macro.
Fixes: b5b5b32081
("i2c: mlxbf: I2C SMBus driver for Mellanox BlueField SoC")
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Khalil Blaiech <kblaiech@nvidia.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
parent
4b19d806ac
commit
67ee9fda6e
1 changed files with 4 additions and 6 deletions
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@ -62,10 +62,8 @@
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* Master. Default value is set to 400MHz.
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*/
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#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
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/* Reference clock for Bluefield 1 - 156 MHz. */
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#define MLXBF_I2C_TYU_PLL_IN_FREQ (156 * 1000 * 1000)
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/* Reference clock for BlueField 2 - 200 MHz. */
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#define MLXBF_I2C_YU_PLL_IN_FREQ (200 * 1000 * 1000)
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/* Reference clock for Bluefield - 156 MHz. */
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#define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000)
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/* Constant used to determine the PLL frequency. */
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#define MLNXBF_I2C_COREPLL_CONST 16384
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@ -1422,7 +1420,7 @@ static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
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u32 corepll_val;
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u16 core_f;
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pad_frequency = MLXBF_I2C_TYU_PLL_IN_FREQ;
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pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
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corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
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@ -1457,7 +1455,7 @@ static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
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u8 core_od, core_r;
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u32 core_f;
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pad_frequency = MLXBF_I2C_YU_PLL_IN_FREQ;
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pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
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corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
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corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
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