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drm/i915/gvt: Introduce per object locking in GVT scheduler.
To support ww locking and per-object implemented in i915, GVT scheduler needs
to be refined. Most of the changes are located in shadow batch buffer, shadow
wa context in GVT-g, where use quite a lot of i915 gem object APIs.
v2:
- Adjust the usage of ww lock on context pin/unpin. (maarten)
- Rebase the patch on the newest staging branch.
Fixes: 6b05030496
("drm/i915: Convert i915_gem_object/client_blt.c to use ww locking as well, v2.")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1610314985-26065-1-git-send-email-zhi.wang.linux@gmail.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
parent
d18ac1a7ee
commit
67f1120381
1 changed files with 40 additions and 9 deletions
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@ -412,7 +412,9 @@ static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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if (!wa_ctx->indirect_ctx.obj)
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return;
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i915_gem_object_lock(wa_ctx->indirect_ctx.obj, NULL);
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i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
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i915_gem_object_unlock(wa_ctx->indirect_ctx.obj);
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i915_gem_object_put(wa_ctx->indirect_ctx.obj);
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wa_ctx->indirect_ctx.obj = NULL;
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@ -520,6 +522,7 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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struct intel_gvt *gvt = workload->vgpu->gvt;
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const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
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struct intel_vgpu_shadow_bb *bb;
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struct i915_gem_ww_ctx ww;
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int ret;
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list_for_each_entry(bb, &workload->shadow_bb, list) {
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@ -544,10 +547,19 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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* directly
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*/
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if (!bb->ppgtt) {
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bb->vma = i915_gem_object_ggtt_pin(bb->obj,
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NULL, 0, 0, 0);
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i915_gem_ww_ctx_init(&ww, false);
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retry:
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i915_gem_object_lock(bb->obj, &ww);
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bb->vma = i915_gem_object_ggtt_pin_ww(bb->obj, &ww,
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NULL, 0, 0, 0);
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if (IS_ERR(bb->vma)) {
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ret = PTR_ERR(bb->vma);
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if (ret == -EDEADLK) {
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ret = i915_gem_ww_ctx_backoff(&ww);
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if (!ret)
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goto retry;
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}
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goto err;
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}
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@ -561,13 +573,15 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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0);
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if (ret)
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goto err;
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}
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/* No one is going to touch shadow bb from now on. */
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i915_gem_object_flush_map(bb->obj);
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/* No one is going to touch shadow bb from now on. */
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i915_gem_object_flush_map(bb->obj);
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i915_gem_object_unlock(bb->obj);
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}
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}
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return 0;
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err:
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i915_gem_ww_ctx_fini(&ww);
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release_shadow_batch_buffer(workload);
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return ret;
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}
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@ -594,14 +608,29 @@ static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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unsigned char *per_ctx_va =
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(unsigned char *)wa_ctx->indirect_ctx.shadow_va +
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wa_ctx->indirect_ctx.size;
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struct i915_gem_ww_ctx ww;
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int ret;
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if (wa_ctx->indirect_ctx.size == 0)
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return 0;
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vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
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0, CACHELINE_BYTES, 0);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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i915_gem_ww_ctx_init(&ww, false);
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retry:
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i915_gem_object_lock(wa_ctx->indirect_ctx.obj, &ww);
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vma = i915_gem_object_ggtt_pin_ww(wa_ctx->indirect_ctx.obj, &ww, NULL,
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0, CACHELINE_BYTES, 0);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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if (ret == -EDEADLK) {
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ret = i915_gem_ww_ctx_backoff(&ww);
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if (!ret)
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goto retry;
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}
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return ret;
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}
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i915_gem_object_unlock(wa_ctx->indirect_ctx.obj);
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/* FIXME: we are not tracking our pinned VMA leaving it
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* up to the core to fix up the stray pin_count upon
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@ -635,12 +664,14 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
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if (bb->obj) {
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i915_gem_object_lock(bb->obj, NULL);
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if (bb->va && !IS_ERR(bb->va))
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i915_gem_object_unpin_map(bb->obj);
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if (bb->vma && !IS_ERR(bb->vma))
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i915_vma_unpin(bb->vma);
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i915_gem_object_unlock(bb->obj);
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i915_gem_object_put(bb->obj);
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}
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list_del(&bb->list);
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