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clk: tegra: Fix PLLD mnp table
PLLD was using the same mnp table as PLLP. Fix it to use its own table which is different from PLLP's. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
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1 changed files with 10 additions and 1 deletions
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@ -570,6 +570,15 @@ static struct tegra_clk_pll_params pll_a_params = {
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.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
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};
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static struct div_nmp plld_nmp = {
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.divm_shift = 0,
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.divm_width = 5,
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.divn_shift = 8,
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.divn_width = 11,
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.divp_shift = 20,
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.divp_width = 3,
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};
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static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
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{12000000, 216000000, 864, 12, 4, 12},
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{13000000, 216000000, 864, 13, 4, 12},
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@ -603,7 +612,7 @@ static struct tegra_clk_pll_params pll_d_params = {
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.lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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.div_nmp = &pllp_nmp,
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.div_nmp = &plld_nmp,
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.freq_table = pll_d_freq_table,
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.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
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TEGRA_PLL_USE_LOCK,
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