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drm/amd/pm: enable DCS
Enable DCS V1: Enable Async DCS. V2: Add the ppfeaturemask bit to enable from the modprobe parameter. V3: 1. add the flag to skip APU support. 2. remove the hunk for workload selection since it doesn't impact the function. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
e83db77487
commit
680602d6c2
3 changed files with 12 additions and 2 deletions
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@ -132,8 +132,12 @@ uint amdgpu_pg_mask = 0xffffffff;
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uint amdgpu_sdma_phase_quantum = 32;
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char *amdgpu_disable_cu = NULL;
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char *amdgpu_virtual_display = NULL;
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/* OverDrive(bit 14) disabled by default*/
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uint amdgpu_pp_feature_mask = 0xffffbfff;
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/*
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* OverDrive(bit 14) disabled by default
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* GFX DCS(bit 19) disabled by default
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*/
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uint amdgpu_pp_feature_mask = 0xfff7bfff;
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uint amdgpu_force_long_training;
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int amdgpu_job_hang_limit;
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int amdgpu_lbpw = -1;
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@ -213,6 +213,7 @@ enum PP_FEATURE_MASK {
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PP_ACG_MASK = 0x10000,
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PP_STUTTER_MODE = 0x20000,
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PP_AVFS_MASK = 0x40000,
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PP_GFX_DCS_MASK = 0x80000,
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};
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enum DC_FEATURE_MASK {
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@ -261,6 +261,11 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
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}
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if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
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(adev->asic_type > CHIP_SIENNA_CICHLID) &&
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!(adev->flags & AMD_IS_APU))
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
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if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
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| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
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