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ALSA: ice1724 - Re-fix IRQ mask initialization
The previous IRQ mask initialization was wrong. It must set the bits to be masked. Signed-off-by: Takashi Iwai <tiwai@suse.de>
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4074ea2149
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1 changed files with 4 additions and 4 deletions
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@ -395,8 +395,8 @@ static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
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"status = 0x%x\n", status);
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if (status & VT1724_IRQ_MPU_TX) {
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printk(KERN_ERR "ice1724: Disabling MPU_TX\n");
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outb(inb(ICEREG1724(ice, IRQMASK)) &
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~VT1724_IRQ_MPU_TX,
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outb(inb(ICEREG1724(ice, IRQMASK)) |
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VT1724_IRQ_MPU_TX,
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ICEREG1724(ice, IRQMASK));
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}
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break;
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@ -2413,8 +2413,8 @@ static int __devinit snd_vt1724_create(struct snd_card *card,
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return -EIO;
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}
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/* clear interrupts -- otherwise you'll get irq problems later */
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outb(0, ICEREG1724(ice, IRQMASK));
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/* MPU_RX and TX irq masks are cleared later dynamically */
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outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
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/* don't handle FIFO overrun/underruns (just yet),
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* since they cause machine lockups
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