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A clock regression fix that happened with the common clock
conversion, and few USB regression fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRUyKkAAoJEBvUPslcq6VzLPYQANRVTd7zZ1Eu8GbgUylb939Q dUBMEZwH+RjAAEXZgVcbvDnyidi+ee/44EDNyRPnPcuV4H7xskVsG9qXnSKyqo8u X+cOEUM+eK8/7zrWTNFvozacDprGPvikrJX9LBPDQfHeQGLqHqtz8yvN47QyknXE M6kxXpY8QtSG6nx/I6+wYJzyI7qsNLbIgd5eTXsRK5FeALbkth5FE32TaKLqUcqH LkBJXp7qrmBLLgYf0pfIG6/a5Re6cQYhcETmJqVE0x8xkJvHT2TZVyaRcqbfU61l olzGCKNDc5uh53IOvpv8xUQZlvEPbhct8gX2ccFnML2/GxvqVjYM05olmJY/V+Hp 1gRcqo6LCUghEpX3aKYrL33XlJtZ2555VD/jETHofHm+9ORiQnmVskL3H5ZQP9VP jB44omxxRT86SUl8LdPqS5L/u90o1CP6KKz1ejyZIrio4QnUGC3YRCAnjclV88U8 lypM11+eNbNW7ug+YA60H8gMPbiEMruhNi6s8JG8KBOFEiJAbTu7ZOrr5nig8bDd 1sHD+5BeQVCEgZ0ivjbbahk//T+SMwvNo6gdVoCKlzLucmKuekpZ/ZvrB83s8Ve4 LlExvPRg7u/RZt+7MiLo+qWmXcPvYSRAVkdHP8sXitCq8WXIQ5uPe0mBbaQCI8fk s5F2EppSvGKlXaq5sLRS =DYTR -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.9-rc3/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes From Tony Lindgren <tony@atomide.com>: A clock regression fix that happened with the common clock conversion, and few USB regression fixes. * tag 'omap-for-v3.9-rc3/fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized ARM: OMAP4: PM: fix PM regression introduced by recent clock cleanup ARM: OMAP3: hwmod data: keep MIDLEMODE in force-standby for musb ARM: OMAP4: clock data: lock USB DPLL on boot ARM: OMAP1: fix USB host on 1710 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
68843129b1
9 changed files with 64 additions and 22 deletions
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@ -538,15 +538,6 @@ static struct clk usb_hhc_ck16xx = {
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};
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static struct clk usb_dc_ck = {
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.name = "usb_dc_ck",
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.ops = &clkops_generic,
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
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.enable_bit = USB_REQ_EN_SHIFT,
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};
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static struct clk usb_dc_ck7xx = {
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.name = "usb_dc_ck",
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.ops = &clkops_generic,
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/* Direct from ULPD, no parent */
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@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
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CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
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CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
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CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
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CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
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CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
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CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
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CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
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CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
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CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
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@ -52,6 +52,13 @@
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*/
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#define OMAP4_DPLL_ABE_DEFFREQ 98304000
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/*
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* OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
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* "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
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* locked frequency for the USB DPLL is 960MHz.
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*/
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#define OMAP4_DPLL_USB_DEFFREQ 960000000
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/* Root clocks */
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DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
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@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
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OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
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hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
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DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
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OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
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OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
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DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
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OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
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OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
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@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
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CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
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CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
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CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
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CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
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CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
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CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
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CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
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@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
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if (rc)
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pr_err("%s: failed to configure ABE DPLL!\n", __func__);
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/*
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* Lock USB DPLL on OMAP4 devices so that the L3INIT power
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* domain can transition to retention state when not in use.
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*/
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rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
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if (rc)
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pr_err("%s: failed to configure USB DPLL!\n", __func__);
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return 0;
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}
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@ -293,5 +293,8 @@ extern void omap_reserve(void);
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struct omap_hwmod;
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extern int omap_dss_reset(struct omap_hwmod *);
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/* SoC specific clock initializer */
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extern int (*omap_clk_init)(void);
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#endif /* __ASSEMBLER__ */
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#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
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@ -54,6 +54,12 @@
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#include "prm3xxx.h"
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#include "prm44xx.h"
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/*
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* omap_clk_init: points to a function that does the SoC-specific
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* clock initializations
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*/
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int (*omap_clk_init)(void);
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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@ -397,7 +403,7 @@ void __init omap2420_init_early(void)
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omap242x_clockdomains_init();
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omap2420_hwmod_init();
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omap_hwmod_init_postsetup();
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omap2420_clk_init();
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omap_clk_init = omap2420_clk_init;
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}
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void __init omap2420_init_late(void)
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@ -427,7 +433,7 @@ void __init omap2430_init_early(void)
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omap243x_clockdomains_init();
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omap2430_hwmod_init();
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omap_hwmod_init_postsetup();
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omap2430_clk_init();
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omap_clk_init = omap2430_clk_init;
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}
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void __init omap2430_init_late(void)
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@ -462,7 +468,7 @@ void __init omap3_init_early(void)
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omap3xxx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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omap3xxx_clk_init();
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omap_clk_init = omap3xxx_clk_init;
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}
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void __init omap3430_init_early(void)
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@ -500,7 +506,7 @@ void __init ti81xx_init_early(void)
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omap3xxx_clockdomains_init();
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omap3xxx_hwmod_init();
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omap_hwmod_init_postsetup();
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omap3xxx_clk_init();
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omap_clk_init = omap3xxx_clk_init;
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}
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void __init omap3_init_late(void)
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@ -568,7 +574,7 @@ void __init am33xx_init_early(void)
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am33xx_clockdomains_init();
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am33xx_hwmod_init();
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omap_hwmod_init_postsetup();
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am33xx_clk_init();
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omap_clk_init = am33xx_clk_init;
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}
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#endif
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@ -593,7 +599,7 @@ void __init omap4430_init_early(void)
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omap44xx_clockdomains_init();
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omap44xx_hwmod_init();
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omap_hwmod_init_postsetup();
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omap4xxx_clk_init();
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omap_clk_init = omap4xxx_clk_init;
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}
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void __init omap4430_init_late(void)
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@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
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}
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if (sf & SYSC_HAS_MIDLEMODE) {
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if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
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if (oh->flags & HWMOD_FORCE_MSTANDBY) {
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idlemode = HWMOD_IDLEMODE_FORCE;
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} else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
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idlemode = HWMOD_IDLEMODE_NO;
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} else {
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if (sf & SYSC_HAS_ENAWAKEUP)
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@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
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}
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if (sf & SYSC_HAS_MIDLEMODE) {
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if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
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if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
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(oh->flags & HWMOD_FORCE_MSTANDBY)) {
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idlemode = HWMOD_IDLEMODE_FORCE;
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} else {
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if (sf & SYSC_HAS_ENAWAKEUP)
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@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
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*
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* HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
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* of idle, rather than relying on module smart-idle
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* HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
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* of standby, rather than relying on module smart-standby
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* HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
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* out of standby, rather than relying on module smart-standby
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* HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
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* SDRAM controller, etc. XXX probably belongs outside the main hwmod file
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* XXX Should be HWMOD_SETUP_NO_RESET
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@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
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* correctly, or this is being abused to deal with some PM latency
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* issues -- but we're currently suffering from a shortage of
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* folks who are able to track these issues down properly.
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* HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
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* is kept in force-standby mode. Failing to do so causes PM problems
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* with musb on OMAP3630 at least. Note that musb has a dedicated register
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* to control MSTANDBY signal when MIDLEMODE is set to force-standby.
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*/
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#define HWMOD_SWSUP_SIDLE (1 << 0)
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#define HWMOD_SWSUP_MSTANDBY (1 << 1)
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@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
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#define HWMOD_16BIT_REG (1 << 8)
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#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
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#define HWMOD_BLOCK_WFI (1 << 10)
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#define HWMOD_FORCE_MSTANDBY (1 << 11)
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/*
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* omap_hwmod._int_flags definitions
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@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
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* Erratum ID: i479 idle_req / idle_ack mechanism potentially
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* broken when autoidle is enabled
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* workaround is to disable the autoidle bit at module level.
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*
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* Enabling the device in any other MIDLEMODE setting but force-idle
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* causes core_pwrdm not enter idle states at least on OMAP3630.
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* Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
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* signal when MIDLEMODE is set to force-idle.
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*/
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.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
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| HWMOD_SWSUP_MSTANDBY,
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| HWMOD_FORCE_MSTANDBY,
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};
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/* usb_otg_hs */
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@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
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{ }
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};
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static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
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{ .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
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};
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/* ocp2scp_usb_phy */
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static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
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.name = "ocp2scp_usb_phy",
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@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
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},
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},
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.dev_attr = ocp2scp_dev_attr,
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.opt_clks = ocp2scp_usb_phy_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
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};
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/*
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@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
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clksrc_nr, clksrc_src) \
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void __init omap##name##_gptimer_timer_init(void) \
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{ \
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if (omap_clk_init) \
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omap_clk_init(); \
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omap_dmtimer_init(); \
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omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
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omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
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@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void) \
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clksrc_nr, clksrc_src) \
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void __init omap##name##_sync32k_timer_init(void) \
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{ \
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if (omap_clk_init) \
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omap_clk_init(); \
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omap_dmtimer_init(); \
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omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
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/* Enable the use of clocksource="gp_timer" kernel parameter */ \
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