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[MIPS] Delete Ocelot 3 support. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2007-07-09 16:29:16 +01:00
parent c99cabf034
commit 688b3d7208
62 changed files with 3 additions and 2732 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
arch/mips/Kconfig
View File

@ -266,25 +266,6 @@ config MOMENCO_OCELOT
The Ocelot is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config MOMENCO_OCELOT_3
bool "Momentum Ocelot-3 board"
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_MV64340
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
help
The Ocelot-3 is based off Discovery III System Controller and
PMC-Sierra Rm79000 core.
config PNX8550_JBS
bool "Philips PNX8550 based JBS board"
select PNX8550
@ -826,9 +807,6 @@ config IRQ_MSP_SLP
config IRQ_MSP_CIC
bool
config IRQ_MV64340
bool
config DDB5XXX_COMMON
bool
select SYS_SUPPORTS_KGDB
@ -850,9 +828,6 @@ config MIPS_RM9122
bool
select SERIAL_RM9000
config PCI_MARVELL
bool
config PNX8550
bool
select SOC_PNX8550

7
arch/mips/Makefile
View File

@ -364,13 +364,6 @@ core-$(CONFIG_QEMU) += arch/mips/qemu/
cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
load-$(CONFIG_QEMU) += 0xffffffff80010000
#
# Momentum Ocelot-3
#
core-$(CONFIG_MOMENCO_OCELOT_3) += arch/mips/momentum/ocelot_3/
cflags-$(CONFIG_MOMENCO_OCELOT_3) += -Iinclude/asm-mips/mach-ocelot3
load-$(CONFIG_MOMENCO_OCELOT_3) += 0xffffffff80100000
#
# Basler eXcite
#

1
arch/mips/configs/atlas_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_MIPS_ATLAS=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/bigsur_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/capcella_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/cobalt_defconfig
View File

@ -19,7 +19,6 @@ CONFIG_MIPS_COBALT=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_DDB5477 is not set

1
arch/mips/configs/db1000_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/db1100_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/db1200_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/db1500_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/db1550_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/ddb5477_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/decstation_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_MACH_DECSTATION=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/e55_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/emma2rh_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/excite_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_BASLER_EXCITE=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/fulong_defconfig
View File

@ -20,7 +20,6 @@ CONFIG_LEMOTE_FULONG=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_DDB5477 is not set

1
arch/mips/configs/ip22_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/ip27_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/ip32_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/jazz_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_MACH_JAZZ=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/jmr3927_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/malta_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_MIPS_MALTA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/mipssim_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
CONFIG_MIPS_SIM=y
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/mpc30x_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/msp71xx_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1280
arch/mips/configs/ocelot_3_defconfig
View File

File diff suppressed because it is too large Load Diff

1
arch/mips/configs/ocelot_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
CONFIG_MOMENCO_OCELOT=y
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/pb1100_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/pb1500_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/pb1550_defconfig
View File

@ -34,7 +34,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/pnx8550-jbs_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
CONFIG_PNX8550_JBS=y

1
arch/mips/configs/pnx8550-stb810_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/qemu_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/rbhma4200_defconfig
View File

@ -31,7 +31,6 @@ CONFIG_MIPS=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set

1
arch/mips/configs/rbhma4500_defconfig
View File

@ -21,7 +21,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_WR_PPMC is not set
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_DDB5477 is not set

1
arch/mips/configs/rm200_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/sb1250-swarm_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/sead_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_MIPS_SEAD=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/tb0219_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/tb0226_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/tb0287_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/workpad_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/wrppmc_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_WR_PPMC=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/configs/yosemite_defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/defconfig
View File

@ -33,7 +33,6 @@ CONFIG_ZONE_DMA=y
# CONFIG_MIPS_SIM is not set
# CONFIG_MOMENCO_JAGUAR_ATX is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_3 is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_JBS is not set

1
arch/mips/kernel/Makefile
View File

@ -49,7 +49,6 @@ obj-$(CONFIG_I8259) += i8259.o
obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o
obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
obj-$(CONFIG_32BIT) += scall32-o32.o

111
arch/mips/kernel/irq-mv6434x.c
View File

@ -1,111 +0,0 @@
/*
* Copyright 2002 Momentum Computer
* Author: mdharm@momenco.com
* Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/kernel_stat.h>
#include <linux/mv643xx.h>
#include <linux/sched.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/marvell.h>
static unsigned int irq_base;
static inline int ls1bit32(unsigned int x)
{
int b = 31, s;
s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
s = 1; if (x << 1 == 0) s = 0; b -= s;
return b;
}
/* mask off an interrupt -- 1 is enable, 0 is disable */
static inline void mask_mv64340_irq(unsigned int irq)
{
uint32_t value;
if (irq < (irq_base + 32)) {
value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
value &= ~(1 << (irq - irq_base));
MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
} else {
value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
value &= ~(1 << (irq - irq_base - 32));
MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
}
}
/* unmask an interrupt -- 1 is enable, 0 is disable */
static inline void unmask_mv64340_irq(unsigned int irq)
{
uint32_t value;
if (irq < (irq_base + 32)) {
value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
value |= 1 << (irq - irq_base);
MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
} else {
value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
value |= 1 << (irq - irq_base - 32);
MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
}
}
/*
* Interrupt handler for interrupts coming from the Marvell chip.
* It could be built in ethernet ports etc...
*/
void ll_mv64340_irq(void)
{
unsigned int irq_src_low, irq_src_high;
unsigned int irq_mask_low, irq_mask_high;
/* read the interrupt status registers */
irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
/* mask for just the interrupts we want */
irq_src_low &= irq_mask_low;
irq_src_high &= irq_mask_high;
if (irq_src_low)
do_IRQ(ls1bit32(irq_src_low) + irq_base);
else
do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
}
struct irq_chip mv64340_irq_type = {
.name = "MV-64340",
.ack = mask_mv64340_irq,
.mask = mask_mv64340_irq,
.mask_ack = mask_mv64340_irq,
.unmask = unmask_mv64340_irq,
};
void __init mv64340_irq_init(unsigned int base)
{
int i;
for (i = base; i < base + 64; i++)
set_irq_chip_and_handler(i, &mv64340_irq_type,
handle_level_irq);
irq_base = base;
}

8
arch/mips/momentum/ocelot_3/Makefile
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@ -1,8 +0,0 @@
#
# Makefile for Momentum Computer's Ocelot-3 board.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y += irq.o platform.o prom.o reset.o setup.o

109
arch/mips/momentum/ocelot_3/irq.c
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@ -1,109 +0,0 @@
/*
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
* Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
*
* Copyright 2004 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
*
*/
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
static struct irqaction cascade_mv64340 = {
no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
};
void __init arch_init_irq(void)
{
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM | ST0_BEV);
rm7k_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */
mv64340_irq_init(16);
set_c0_status(ST0_IM); /* IE in the status register */
}
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & STATUSF_IP0)
do_IRQ(0);
else if (pending & STATUSF_IP1)
do_IRQ(1);
else if (pending & STATUSF_IP2)
do_IRQ(2);
else if (pending & STATUSF_IP3)
do_IRQ(3);
else if (pending & STATUSF_IP4)
do_IRQ(4);
else if (pending & STATUSF_IP5)
do_IRQ(5);
else if (pending & STATUSF_IP6)
do_IRQ(6);
else if (pending & STATUSF_IP7)
do_IRQ(7);
else {
/*
* Now look at the extended interrupts
*/
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
if (pending & STATUSF_IP8)
ll_mv64340_irq();
else
spurious_interrupt();
}
}

59
arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
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@ -1,59 +0,0 @@
/*
* Ocelot-3 Board Register Definitions
*
* (C) 2002 Momentum Computer Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
*/
#ifndef __OCELOT_3_FPGA_H__
#define __OCELOT_3_FPGA_H__
#define OCELOT_3_REG_BOARDREV 0x0
#define OCELOT_3_REG_FPGA_REV 0x1
#define OCELOT_3_REG_FPGA_TYPE 0x2
#define OCELOT_3_REG_RESET_STATUS 0x3
#define OCELOT_3_REG_BOARD_STATUS 0x4
#define OCELOT_3_REG_CPCI_ID 0x5
#define OCELOT_3_REG_SET 0x6
#define OCELOT_3_REG_CLR 0x7
#define OCELOT_3_REG_EEPROM_MODE 0x9
#define OCELOT_3_REG_INTMASK 0xa
#define OCELOT_3_REG_INTSTAT 0xb
#define OCELOT_3_REG_UART_INTMASK 0xc
#define OCELOT_3_REG_UART_INTSTAT 0xd
#define OCELOT_3_REG_INTSET 0xe
#define OCELOT_3_REG_INTCLR 0xf
extern unsigned long ocelot_fpga_base;
#define __FPGA_REG_TO_ADDR(reg) \
((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif

252
arch/mips/momentum/ocelot_3/platform.c
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@ -1,252 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
* Copyright (C) 2007 Dale Farnsworth (dale@farnsworth.org)
*/
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include "ocelot_3_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
#define MV64x60_IRQ_ETH_2 50
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth0_pd = {
.port_number = 0,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth1_pd = {
.port_number = 1,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
static struct resource mv64x60_eth2_resources[] = {
[0] = {
.name = "eth2 irq",
.start = MV64x60_IRQ_ETH_2,
.end = MV64x60_IRQ_ETH_2,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth2_pd = {
.port_number = 2,
};
static struct platform_device eth2_device = {
.name = MV643XX_ETH_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
.resource = mv64x60_eth2_resources,
.dev = {
.platform_data = &eth2_pd,
},
};
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
&eth0_device,
&eth1_device,
&eth2_device,
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
eth_mac_add(eth0_pd.mac_addr, mac, 0);
eth_mac_add(eth1_pd.mac_addr, mac, 1);
eth_mac_add(eth2_pd.mac_addr, mac, 2);
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
#define OCELOT3_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
static struct plat_serial8250_port uart8250_data[] = {
{
.membase = (signed long) 0xfd000020,
.irq = 6,
.uartclk = 20000000,
.iotype = UPIO_MEM,
.flags = OCELOT3_UART_FLAGS,
.regshift = 2,
},
{ },
};
static struct platform_device uart8250_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = uart8250_data,
},
};
static int __init uart8250_init(void)
{
return platform_device_register(&uart8250_device);
}
module_init(uart8250_init);
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("8250 UART probe driver for the Ocelot 3");

189
arch/mips/momentum/ocelot_3/prom.c
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@ -1,189 +0,0 @@
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Copyright 2004 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* Based on Ocelot Linux port, which is
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
*
*/
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#include "ocelot_3_fpga.h"
struct callvectors* debug_vectors;
extern unsigned long marvell_base;
extern unsigned long cpu_clock;
const char *get_system_type(void)
{
return "Momentum Ocelot-3";
}
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
{
addr &= 0xffffffff;
return (unsigned long)((int)addr);
}
void *get_arg(unsigned long args, int arc)
{
unsigned long ul;
unsigned char *puc, uc;
args += (arc * 4);
ul = (unsigned long)signext(args);
puc = (unsigned char *)ul;
if (puc == 0)
return (void *)0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
uc = *puc++;
ul = (unsigned long)uc;
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 24);
#else /* CONFIG_CPU_LITTLE_ENDIAN */
uc = *puc++;
ul = ((unsigned long)uc) << 24;
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= ((unsigned long)uc);
#endif /* CONFIG_CPU_LITTLE_ENDIAN */
ul = signext(ul);
return (void *)ul;
}
char *arg64(unsigned long addrin, int arg_index)
{
unsigned long args;
char *p;
args = signext(addrin);
p = (char *)get_arg(args, arg_index);
return p;
}
#endif /* CONFIG_64BIT */
void __init prom_init(void)
{
int argc = fw_arg0;
char **arg = (char **) fw_arg1;
char **env = (char **) fw_arg2;
struct callvectors *cv = (struct callvectors *) fw_arg3;
int i;
#ifdef CONFIG_64BIT
char *ptr;
printk("prom_init - MIPS64\n");
/* save the PROM vectors for debugging use */
debug_vectors = (struct callvectors *)signext((unsigned long)cv);
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
ptr = (char *)arg64((unsigned long)arg, i);
if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, ptr);
strcat(arcs_cmdline, " ");
}
i = 0;
while (1) {
ptr = (char *)arg64((unsigned long)env, i);
if (! ptr)
break;
if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(ptr + strlen("gtbase="),
NULL, 16);
if ((marvell_base & 0xffffffff00000000) == 0)
marvell_base |= 0xffffffff00000000;
printk("marvell_base set to 0x%016lx\n", marvell_base);
}
if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
NULL, 10);
printk("cpu_clock set to %d\n", cpu_clock);
}
i++;
}
printk("arcs_cmdline: %s\n", arcs_cmdline);
#else /* CONFIG_64BIT */
/* save the PROM vectors for debugging use */
debug_vectors = cv;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
while (*env) {
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(*env + strlen("gtbase="),
NULL, 16);
}
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(*env + strlen("cpuclock="),
NULL, 10);
}
env++;
}
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_OCELOT_3;
#ifndef CONFIG_64BIT
debug_vectors->printf("Booting Linux kernel...\n");
#endif
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}

59
arch/mips/momentum/ocelot_3/reset.c
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@ -1,59 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 01, 05 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Copyright 2004 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
void momenco_ocelot_restart(char *command)
{
/* base address of timekeeper portion of part */
void *nvram = (void *) 0xfc807000L;
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
mdelay(100+(1000/16));
/* if the watchdog fails for some reason, let people know */
printk(KERN_NOTICE "Watchdog reset failed\n");
}
void momenco_ocelot_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void momenco_ocelot_power_off(void)
{
momenco_ocelot_halt();
}

398
arch/mips/momentum/ocelot_3/setup.c
View File

@ -1,398 +0,0 @@
/*
* setup.c
*
* BRIEF MODULE DESCRIPTION
* Momentum Computer Ocelot-3 board dependent boot routines
*
* Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
* Copyright (C) 2000 RidgeRun, Inc.
* Copyright (C) 2001 Red Hat, Inc.
* Copyright (C) 2002 Momentum Computer
*
* Author: Matthew Dharm, Momentum Computer
* mdharm@momenco.com
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright 2004 PMC-Sierra
* Author: Manish Lachwani (lachwani@pmc-sierra.com)
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/mc146818rtc.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/timex.h>
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
#include <linux/pm.h>
#include <linux/bcd.h>
#include <asm/time.h>
#include <asm/page.h>
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pci.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/mc146818rtc.h>
#include <asm/tlbflush.h>
#include "ocelot_3_fpga.h"
/* Marvell Discovery Register Base */
unsigned long marvell_base = (signed)0xf4000000;
/* CPU clock */
unsigned long cpu_clock;
/* RTC/NVRAM */
unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
/* FPGA Base */
unsigned long ocelot_fpga_base = (signed)0xfc000000;
/* Serial base */
unsigned long uart_base = (signed)0xfd000000;
/*
* Marvell Discovery SRAM. This is one place where Ethernet
* Tx and Rx descriptors can be placed to improve performance
*/
extern unsigned long mv64340_sram_base;
/* These functions are used for rebooting or halting the machine*/
extern void momenco_ocelot_restart(char *command);
extern void momenco_ocelot_halt(void);
extern void momenco_ocelot_power_off(void);
void momenco_time_init(void);
static char reset_reason;
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
unsigned long entryhi, unsigned long pagemask);
static inline unsigned long ENTRYLO(unsigned long paddr)
{
return ((paddr & PAGE_MASK) |
(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
_CACHE_UNCACHED)) >> 6;
}
void __init bus_error_init(void)
{
/* nothing */
}
/*
* setup code for a handoff from a version 2 PMON 2000 PROM
*/
void setup_wired_tlb_entries(void)
{
write_c0_wired(0);
local_flush_tlb_all();
/* marvell and extra space */
add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
/* fpga, rtc, and uart */
add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
}
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
year = BCD2BIN(rtc_base[0x7fff]);
year += BCD2BIN(rtc_base[0x7ff1]) * 100;
month = BCD2BIN(rtc_base[0x7ffe]);
day = BCD2BIN(rtc_base[0x7ffd]);
hour = BCD2BIN(rtc_base[0x7ffb]);
min = BCD2BIN(rtc_base[0x7ffa]);
sec = BCD2BIN(rtc_base[0x7ff9]);
/* start the update */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
int m48t37y_set_time(unsigned long sec)
{
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
/* year */
rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
/* month */
rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
/* day */
rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
/* hour/min/sec */
rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
/* day of week -- not really used, but let's keep it up-to-date */
rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
/* disable writing */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
void __init plat_timer_setup(struct irqaction *irq)
{
setup_irq(7, irq); /* Timer interrupt, unmask status IM7 */
}
void momenco_time_init(void)
{
setup_wired_tlb_entries();
/*
* Ocelot-3 board has been built with both
* the Rm7900 and the Rm7065C
*/
mips_hpt_frequency = cpu_clock / 2;
rtc_mips_get_time = m48t37y_get_time;
rtc_mips_set_time = m48t37y_set_time;
}
/*
* PCI Support for Ocelot-3
*/
/* Bus #0 IO and MEM space */
#define OCELOT_3_PCI_IO_0_START 0xe0000000
#define OCELOT_3_PCI_IO_0_SIZE 0x08000000
#define OCELOT_3_PCI_MEM_0_START 0xc0000000
#define OCELOT_3_PCI_MEM_0_SIZE 0x10000000
/* Bus #1 IO and MEM space */
#define OCELOT_3_PCI_IO_1_START 0xe8000000
#define OCELOT_3_PCI_IO_1_SIZE 0x08000000
#define OCELOT_3_PCI_MEM_1_START 0xd0000000
#define OCELOT_3_PCI_MEM_1_SIZE 0x10000000
static struct resource mv_pci_io_mem0_resource = {
.name = "MV64340 PCI0 IO MEM",
.start = OCELOT_3_PCI_IO_0_START,
.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
.flags = IORESOURCE_IO,
};
static struct resource mv_pci_io_mem1_resource = {
.name = "MV64340 PCI1 IO MEM",
.start = OCELOT_3_PCI_IO_1_START,
.end = OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
.flags = IORESOURCE_IO,
};
static struct resource mv_pci_mem0_resource = {
.name = "MV64340 PCI0 MEM",
.start = OCELOT_3_PCI_MEM_0_START,
.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct resource mv_pci_mem1_resource = {
.name = "MV64340 PCI1 MEM",
.start = OCELOT_3_PCI_MEM_1_START,
.end = OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct mv_pci_controller mv_bus0_controller = {
.pcic = {
.pci_ops = &mv_pci_ops,
.mem_resource = &mv_pci_mem0_resource,
.io_resource = &mv_pci_io_mem0_resource,
},
.config_addr = MV64340_PCI_0_CONFIG_ADDR,
.config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
};
static struct mv_pci_controller mv_bus1_controller = {
.pcic = {
.pci_ops = &mv_pci_ops,
.mem_resource = &mv_pci_mem1_resource,
.io_resource = &mv_pci_io_mem1_resource,
},
.config_addr = MV64340_PCI_1_CONFIG_ADDR,
.config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
};
static __init int __init ja_pci_init(void)
{
uint32_t enable;
extern int pci_probe_only;
/* PMON will assign PCI resources */
pci_probe_only = 1;
enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
/*
* We require at least one enabled I/O or PCI memory window or we
* will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
*/
if (enable & (0x01 << 9) || enable & (0x01 << 10))
register_pci_controller(&mv_bus0_controller.pcic);
if (enable & (0x01 << 14) || enable & (0x01 << 15))
register_pci_controller(&mv_bus1_controller.pcic);
ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
OCELOT_3_PCI_IO_1_SIZE - 1;
iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
OCELOT_3_PCI_MEM_1_SIZE - 1;
set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
return 0;
}
arch_initcall(ja_pci_init);
void __init plat_mem_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
pm_power_off = momenco_ocelot_power_off;
/* Wired TLB entries */
setup_wired_tlb_entries();
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
tmpword = OCELOT_FPGA_READ(BOARDREV);
if (tmpword < 26)
printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
tmpword);
tmpword = OCELOT_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x4:
printk(" - cPCI bus reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - Software reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_FPGA_READ(CPCI_ID);
printk("cPCI ID register: 0x%02x\n", tmpword);
printk(" - Slot number: %d\n", tmpword & 0x1f);
printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
/* Support for 128 MB memory */
add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
}

2
arch/mips/pci/Makefile
View File

@ -9,7 +9,6 @@ obj-y += pci.o pci-dac.o
#
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
@ -29,7 +28,6 @@ obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o

41
arch/mips/pci/fixup-ocelot3.c
View File

@ -1,41 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Montavista Software Inc.
* Author: Manish Lachwani (mlachwani@mvista.com)
*
* Looking at the schematics for the Ocelot-3 board, there are
* two PCI busses and each bus has two PCI slots.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/mipsregs.h>
/*
* Do platform specific device initialization at
* pci_enable_device() time
*/
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int bus = dev->bus->number;
if (bus == 0 && slot == 1)
return 2; /* PCI-X A */
if (bus == 0 && slot == 2)
return 3; /* PCI-X B */
if (bus == 1 && slot == 1)
return 4; /* PCI A */
if (bus == 1 && slot == 2)
return 5; /* PCI B */
return 0;
panic("Whooops in pcibios_map_irq");
}

93
arch/mips/pci/ops-marvell.c
View File

@ -1,93 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/marvell.h>
static int mv_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
struct mv_pci_controller *mvbc = bus->sysdata;
unsigned long address_reg, data_reg;
u32 address;
address_reg = mvbc->config_addr;
data_reg = mvbc->config_vreg;
/* Accessing device 31 crashes those Marvells. Since years.
Will they ever make sane controllers ... */
if (PCI_SLOT(devfn) == 31)
return PCIBIOS_DEVICE_NOT_FOUND;
address = (bus->number << 16) | (devfn << 8) |
(where & 0xfc) | 0x80000000;
/* start the configuration cycle */
MV_WRITE(address_reg, address);
switch (size) {
case 1:
*val = MV_READ_8(data_reg + (where & 0x3));
break;
case 2:
*val = MV_READ_16(data_reg + (where & 0x3));
break;
case 4:
*val = MV_READ(data_reg);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int mv_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
struct mv_pci_controller *mvbc = bus->sysdata;
unsigned long address_reg, data_reg;
u32 address;
address_reg = mvbc->config_addr;
data_reg = mvbc->config_vreg;
/* Accessing device 31 crashes those Marvells. Since years.
Will they ever make sane controllers ... */
if (PCI_SLOT(devfn) == 31)
return PCIBIOS_DEVICE_NOT_FOUND;
address = (bus->number << 16) | (devfn << 8) |
(where & 0xfc) | 0x80000000;
/* start the configuration cycle */
MV_WRITE(address_reg, address);
switch (size) {
case 1:
MV_WRITE_8(data_reg + (where & 0x3), val);
break;
case 2:
MV_WRITE_16(data_reg + (where & 0x3), val);
break;
case 4:
MV_WRITE(data_reg, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops mv_pci_ops = {
.read = mv_read_config,
.write = mv_write_config
};

2
drivers/net/Kconfig
View File

@ -2307,7 +2307,7 @@ config UGETH_TX_ON_DEMAND
config MV643XX_ETH
tristate "MV-643XX Ethernet support"
depends on MV64360 || MV64X60 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32)
depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32)
select MII
help
This driver supports the gigabit Ethernet on the Marvell MV643XX

48
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
View File

@ -1,48 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 MontaVista Software Inc.
* Author: Manish Lachwani, mlachwani@mvista.com
* Copyright (C) 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
/*
* Momentum Ocelot-3 is based on Rm7900 processor which
* is based on the E9000 core.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */

4
include/asm-mips/war.h
View File

@ -183,8 +183,8 @@
*/
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
defined(CONFIG_MOMENCO_OCELOT_3) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
defined(CONFIG_WR_PPMC)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif

4
include/linux/mv643xx.h
View File

@ -13,10 +13,6 @@
#ifndef __ASM_MV643XX_H
#define __ASM_MV643XX_H
#ifdef __mips__
#include <asm/addrspace.h>
#include <asm/marvell.h>
#endif
#include <asm/types.h>
/****************************************/