From 942501661fa65f13bf9b5582e8248e92770b2d93 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Thu, 24 Mar 2022 17:38:48 +0530 Subject: [PATCH 1/4] soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194 Add nvmem cell lookup entries for below FUSE cells: - gcplex-config-fuse - pdi0 - pdi1 Also include the device name prefix "gpu-" in the names of the GPU FUSE cells in nvmem_cell_info. Signed-off-by: Sagar Kamble Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 8 ++++---- drivers/soc/tegra/fuse/fuse-tegra30.c | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index aa94fda282f4..b0a8405dbdb1 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. */ #include @@ -162,7 +162,7 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bit_offset = 0, .nbits = 32, }, { - .name = "gcplex-config-fuse", + .name = "gpu-gcplex-config-fuse", .offset = 0x1c8, .bytes = 4, .bit_offset = 0, @@ -186,13 +186,13 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bit_offset = 0, .nbits = 32, }, { - .name = "pdi0", + .name = "gpu-pdi0", .offset = 0x300, .bytes = 4, .bit_offset = 0, .nbits = 32, }, { - .name = "pdi1", + .name = "gpu-pdi1", .offset = 0x304, .bytes = 4, .bit_offset = 0, diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index b071d433d74f..f01d8a2547b6 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. */ #include @@ -344,6 +344,21 @@ static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { .cell_name = "xusb-pad-calibration-ext", .dev_id = "3520000.padctl", .con_id = "calibration-ext", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-gcplex-config-fuse", + .dev_id = "17000000.gpu", + .con_id = "gcplex-config-fuse", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-pdi0", + .dev_id = "17000000.gpu", + .con_id = "pdi0", + }, { + .nvmem_name = "fuse", + .cell_name = "gpu-pdi1", + .dev_id = "17000000.gpu", + .con_id = "pdi1", }, }; From d3ed7526543db9d26341b9df97064b332262b626 Mon Sep 17 00:00:00 2001 From: Sandipan Patra Date: Fri, 1 Apr 2022 20:03:43 +0530 Subject: [PATCH 2/4] soc/tegra: pmc: Update Tegra234 reset sources Update the tegra234_reset_sources array to contain all reset sources for Tegra234 and NULL out the entries that do not actually exist. Signed-off-by: Sandipan Patra Reviewed-by: Andy Shevchenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fdf508e03400..c01db5309b5e 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3766,7 +3766,7 @@ static const struct tegra_pmc_regs tegra234_pmc_regs = { }; static const char * const tegra234_reset_sources[] = { - "SYS_RESET_N", + "SYS_RESET_N", /* 0x0 */ "AOWDT", "BCCPLEXWDT", "BPMPWDT", @@ -3774,19 +3774,36 @@ static const char * const tegra234_reset_sources[] = { "SPEWDT", "APEWDT", "LCCPLEXWDT", - "SENSOR", - "AOTAG", - "VFSENSOR", + "SENSOR", /* 0x8 */ + NULL, + NULL, "MAINSWRST", "SC7", "HSM", - "CSITE", + NULL, "RCEWDT", - "PVA0WDT", - "PVA1WDT", - "L1A_ASYNC", + NULL, /* 0x10 */ + NULL, + NULL, "BPMPBOOT", "FUSECRC", + "DCEWDT", + "PSCWDT", + "PSC", + "CSITE_SW", /* 0x18 */ + "POD", + "SCPM", + "VREFRO_POWERBAD", + "VMON", + "FMON", + "FSI_R5WDT", + "FSI_THERM", + "FSI_R52C0WDT", /* 0x20 */ + "FSI_R52C1WDT", + "FSI_R52C2WDT", + "FSI_R52C3WDT", + "FSI_FMON", + "FSI_VMON", /* 0x25 */ }; static const struct tegra_wake_event tegra234_wake_events[] = { From 9767d1be1529c40469d1bbdc457953f88fa1dca7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 4 May 2022 11:08:14 +0200 Subject: [PATCH 3/4] soc/tegra: pmc: Select REGMAP Commit 9d5e7c3e36eb ("soc/tegra: pmc: Provide USB sleepwalk register map") introduced a dependency on the regmap infrastructure, so select the corresponding Kconfig entry. This avoids failures in random builds that may otherwise end up having SOC_TEGRA_PMC enabled but not REGMAP. Signed-off-by: Thierry Reding --- drivers/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 8b53ed1cc67e..5725c8ef0406 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -146,6 +146,7 @@ config SOC_TEGRA_PMC select GENERIC_PINCONF select PM_OPP select PM_GENERIC_DOMAINS + select REGMAP config SOC_TEGRA_POWERGATE_BPMP def_bool y From d3a20dcbca4880ada8974b2d0167df99161bbfaf Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 6 May 2022 10:53:15 +0200 Subject: [PATCH 4/4] soc/tegra: pmc: Document core domain fields These fields are used to track the state of the core domain. Add basic descriptions so that kerneldoc can be properly generated for them. Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index c01db5309b5e..c77ecf61818b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -394,6 +394,8 @@ struct tegra_pmc_soc { * @domain: IRQ domain provided by the PMC * @irq: chip implementation for the IRQ domain * @clk_nb: pclk clock changes handler + * @core_domain_state_synced: flag marking the core domain's state as synced + * @core_domain_registered: flag marking the core domain as registered */ struct tegra_pmc { struct device *dev;