um: add PCI over virtio emulation driver
To support testing of PCI/PCIe drivers in UML, add a PCI bus support driver. This driver uses virtio, which in UML is really just vhost-user, to talk to devices, and adds the devices to the virtual PCI bus in the system. Since virtio already allows DMA/bus mastering this really isn't all that hard, of course we need the logic_iomem infrastructure that was added by a previous patch. The protocol to talk to the device is has a few fairly simple messages for reading to/writing from config and IO spaces, and messages for the device to send the various interrupts (INT#, MSI/MSI-X and while suspended PME#). Note that currently no offical virtio device ID is assigned for this protocol, as a consequence this patch requires defining it in the Kconfig, with a default that makes the driver refuse to work at all. Finally, in order to add support for MSI/MSI-X interrupts, some small changes are needed in the UML IRQ code, it needs to have more interrupts, changing NR_IRQS from 64 to 128 if this driver is enabled, but not actually use them for anything so that the generic IRQ domain/MSI infrastructure can allocate IRQ numbers. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Richard Weinberger <richard@nod.at>
This commit is contained in:
Johannes Berg
Richard Weinberger
parent
a5ab7c8467
commit
68f5d3f3b6
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@ -15,7 +15,7 @@ config UML
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select HAVE_FUTEX_CMPXCHG if FUTEX
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select HAVE_DEBUG_KMEMLEAK
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select HAVE_DEBUG_BUGVERBOSE
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select NO_DMA
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select NO_DMA if !UML_DMA_EMULATION
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select GENERIC_IRQ_SHOW
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select GENERIC_CPU_DEVICES
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select HAVE_GCC_PLUGINS
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@ -26,10 +26,21 @@ config MMU
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bool
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default y
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config UML_DMA_EMULATION
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bool
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config NO_IOMEM
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bool "disable IOMEM" if EXPERT
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depends on !INDIRECT_IOMEM
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default y
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config UML_IOMEM_EMULATION
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bool
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select INDIRECT_IOMEM
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select GENERIC_PCI_IOMAP
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select GENERIC_IOMAP
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select NO_GENERIC_PCI_IOPORT_MAP
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config NO_IOPORT_MAP
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def_bool y
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@ -357,3 +357,23 @@ config UML_RTC
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rtcwake, especially in time-travel mode. This driver enables that
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by providing a fake RTC clock that causes a wakeup at the right
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time.
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config UML_PCI_OVER_VIRTIO
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bool "Enable PCI over VIRTIO device simulation"
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# in theory, just VIRTIO is enough, but that causes recursion
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depends on VIRTIO_UML
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select FORCE_PCI
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select UML_IOMEM_EMULATION
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select UML_DMA_EMULATION
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select PCI_MSI
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select PCI_MSI_IRQ_DOMAIN
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select PCI_LOCKLESS_CONFIG
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config UML_PCI_OVER_VIRTIO_DEVICE_ID
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int "set the virtio device ID for PCI emulation"
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default -1
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depends on UML_PCI_OVER_VIRTIO
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help
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There's no official device ID assigned (yet), set the one you
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wish to use for experimentation here. The default of -1 is
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not valid and will cause the driver to fail at probe.
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@ -64,6 +64,7 @@ obj-$(CONFIG_BLK_DEV_COW_COMMON) += cow_user.o
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obj-$(CONFIG_UML_RANDOM) += random.o
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obj-$(CONFIG_VIRTIO_UML) += virtio_uml.o
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obj-$(CONFIG_UML_RTC) += rtc.o
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obj-$(CONFIG_UML_PCI_OVER_VIRTIO) += virt-pci.o
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# pcap_user.o must be added explicitly.
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USER_OBJS := fd.o null.o pty.o tty.o xterm.o slip_common.o pcap_user.o vde_user.o vector_user.o
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@ -0,0 +1,885 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Intel Corporation
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* Author: Johannes Berg <johannes@sipsolutions.net>
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/virtio.h>
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#include <linux/virtio_config.h>
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#include <linux/logic_iomem.h>
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#include <linux/irqdomain.h>
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#include <linux/virtio_pcidev.h>
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#include <linux/delay.h>
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#include <linux/msi.h>
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#include <asm/unaligned.h>
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#include <irq_kern.h>
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#define MAX_DEVICES 8
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#define MAX_MSI_VECTORS 32
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#define CFG_SPACE_SIZE 4096
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/* for MSI-X we have a 32-bit payload */
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#define MAX_IRQ_MSG_SIZE (sizeof(struct virtio_pcidev_msg) + sizeof(u32))
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#define NUM_IRQ_MSGS 10
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#define HANDLE_NO_FREE(ptr) ((void *)((unsigned long)(ptr) | 1))
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#define HANDLE_IS_NO_FREE(ptr) ((unsigned long)(ptr) & 1)
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struct um_pci_device {
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struct virtio_device *vdev;
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/* for now just standard BARs */
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u8 resptr[PCI_STD_NUM_BARS];
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struct virtqueue *cmd_vq, *irq_vq;
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#define UM_PCI_STAT_WAITING 0
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unsigned long status;
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int irq;
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};
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struct um_pci_device_reg {
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struct um_pci_device *dev;
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void __iomem *iomem;
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};
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static struct pci_host_bridge *bridge;
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static DEFINE_MUTEX(um_pci_mtx);
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static struct um_pci_device_reg um_pci_devices[MAX_DEVICES];
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static struct fwnode_handle *um_pci_fwnode;
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static struct irq_domain *um_pci_inner_domain;
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static struct irq_domain *um_pci_msi_domain;
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static unsigned long um_pci_msi_used[BITS_TO_LONGS(MAX_MSI_VECTORS)];
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#define UM_VIRT_PCI_MAXDELAY 40000
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static int um_pci_send_cmd(struct um_pci_device *dev,
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struct virtio_pcidev_msg *cmd,
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unsigned int cmd_size,
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const void *extra, unsigned int extra_size,
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void *out, unsigned int out_size)
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{
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struct scatterlist out_sg, extra_sg, in_sg;
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struct scatterlist *sgs_list[] = {
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[0] = &out_sg,
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[1] = extra ? &extra_sg : &in_sg,
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[2] = extra ? &in_sg : NULL,
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};
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int delay_count = 0;
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int ret, len;
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bool posted;
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if (WARN_ON(cmd_size < sizeof(*cmd)))
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return -EINVAL;
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switch (cmd->op) {
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case VIRTIO_PCIDEV_OP_CFG_WRITE:
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case VIRTIO_PCIDEV_OP_MMIO_WRITE:
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case VIRTIO_PCIDEV_OP_MMIO_MEMSET:
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/* in PCI, writes are posted, so don't wait */
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posted = !out;
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WARN_ON(!posted);
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break;
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default:
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posted = false;
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break;
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}
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if (posted) {
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u8 *ncmd = kmalloc(cmd_size + extra_size, GFP_ATOMIC);
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if (ncmd) {
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memcpy(ncmd, cmd, cmd_size);
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if (extra)
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memcpy(ncmd + cmd_size, extra, extra_size);
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cmd = (void *)ncmd;
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cmd_size += extra_size;
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extra = NULL;
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extra_size = 0;
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} else {
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/* try without allocating memory */
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posted = false;
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}
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}
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sg_init_one(&out_sg, cmd, cmd_size);
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if (extra)
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sg_init_one(&extra_sg, extra, extra_size);
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if (out)
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sg_init_one(&in_sg, out, out_size);
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/* add to internal virtio queue */
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ret = virtqueue_add_sgs(dev->cmd_vq, sgs_list,
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extra ? 2 : 1,
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out ? 1 : 0,
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posted ? cmd : HANDLE_NO_FREE(cmd),
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GFP_ATOMIC);
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if (ret)
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return ret;
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if (posted) {
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virtqueue_kick(dev->cmd_vq);
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return 0;
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}
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/* kick and poll for getting a response on the queue */
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set_bit(UM_PCI_STAT_WAITING, &dev->status);
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virtqueue_kick(dev->cmd_vq);
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while (1) {
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void *completed = virtqueue_get_buf(dev->cmd_vq, &len);
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if (completed == HANDLE_NO_FREE(cmd))
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break;
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if (WARN_ONCE(virtqueue_is_broken(dev->cmd_vq) ||
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++delay_count > UM_VIRT_PCI_MAXDELAY,
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"um virt-pci delay: %d", delay_count)) {
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ret = -EIO;
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break;
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}
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udelay(1);
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}
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clear_bit(UM_PCI_STAT_WAITING, &dev->status);
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return ret;
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}
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static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset,
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int size)
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{
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struct um_pci_device_reg *reg = priv;
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struct um_pci_device *dev = reg->dev;
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struct virtio_pcidev_msg hdr = {
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.op = VIRTIO_PCIDEV_OP_CFG_READ,
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.size = size,
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.addr = offset,
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};
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/* maximum size - we may only use parts of it */
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u8 data[8];
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if (!dev)
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return ~0ULL;
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memset(data, 0xff, sizeof(data));
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef CONFIG_64BIT
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case 8:
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#endif
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break;
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default:
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WARN(1, "invalid config space read size %d\n", size);
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return ~0ULL;
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}
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if (um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0,
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data, sizeof(data)))
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return ~0ULL;
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switch (size) {
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case 1:
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return data[0];
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case 2:
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return le16_to_cpup((void *)data);
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case 4:
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return le32_to_cpup((void *)data);
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#ifdef CONFIG_64BIT
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case 8:
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return le64_to_cpup((void *)data);
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#endif
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default:
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return ~0ULL;
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}
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}
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static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size,
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unsigned long val)
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{
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struct um_pci_device_reg *reg = priv;
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struct um_pci_device *dev = reg->dev;
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struct {
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struct virtio_pcidev_msg hdr;
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/* maximum size - we may only use parts of it */
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u8 data[8];
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} msg = {
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.hdr = {
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.op = VIRTIO_PCIDEV_OP_CFG_WRITE,
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.size = size,
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.addr = offset,
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},
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};
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if (!dev)
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return;
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switch (size) {
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case 1:
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msg.data[0] = (u8)val;
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break;
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case 2:
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put_unaligned_le16(val, (void *)msg.data);
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break;
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case 4:
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put_unaligned_le32(val, (void *)msg.data);
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break;
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#ifdef CONFIG_64BIT
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case 8:
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put_unaligned_le64(val, (void *)msg.data);
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break;
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#endif
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default:
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WARN(1, "invalid config space write size %d\n", size);
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return;
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}
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WARN_ON(um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0));
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}
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static const struct logic_iomem_ops um_pci_device_cfgspace_ops = {
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.read = um_pci_cfgspace_read,
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.write = um_pci_cfgspace_write,
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};
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static void um_pci_bar_copy_from(void *priv, void *buffer,
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unsigned int offset, int size)
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{
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u8 *resptr = priv;
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struct um_pci_device *dev = container_of(resptr - *resptr,
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struct um_pci_device,
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resptr[0]);
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struct virtio_pcidev_msg hdr = {
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.op = VIRTIO_PCIDEV_OP_MMIO_READ,
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.bar = *resptr,
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.size = size,
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.addr = offset,
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};
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memset(buffer, 0xff, size);
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um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, buffer, size);
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}
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static unsigned long um_pci_bar_read(void *priv, unsigned int offset,
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int size)
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{
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/* maximum size - we may only use parts of it */
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u8 data[8];
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switch (size) {
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case 1:
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case 2:
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case 4:
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#ifdef CONFIG_64BIT
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case 8:
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#endif
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break;
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default:
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WARN(1, "invalid config space read size %d\n", size);
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return ~0ULL;
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}
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um_pci_bar_copy_from(priv, data, offset, size);
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switch (size) {
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case 1:
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return data[0];
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case 2:
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return le16_to_cpup((void *)data);
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case 4:
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return le32_to_cpup((void *)data);
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#ifdef CONFIG_64BIT
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case 8:
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return le64_to_cpup((void *)data);
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#endif
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default:
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return ~0ULL;
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}
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}
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static void um_pci_bar_copy_to(void *priv, unsigned int offset,
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const void *buffer, int size)
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{
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u8 *resptr = priv;
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struct um_pci_device *dev = container_of(resptr - *resptr,
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struct um_pci_device,
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resptr[0]);
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struct virtio_pcidev_msg hdr = {
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.op = VIRTIO_PCIDEV_OP_MMIO_WRITE,
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.bar = *resptr,
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.size = size,
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.addr = offset,
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};
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um_pci_send_cmd(dev, &hdr, sizeof(hdr), buffer, size, NULL, 0);
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}
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static void um_pci_bar_write(void *priv, unsigned int offset, int size,
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unsigned long val)
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{
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/* maximum size - we may only use parts of it */
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u8 data[8];
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switch (size) {
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case 1:
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data[0] = (u8)val;
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break;
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case 2:
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put_unaligned_le16(val, (void *)data);
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break;
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case 4:
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put_unaligned_le32(val, (void *)data);
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break;
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#ifdef CONFIG_64BIT
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case 8:
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put_unaligned_le64(val, (void *)data);
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break;
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#endif
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default:
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WARN(1, "invalid config space write size %d\n", size);
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return;
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}
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um_pci_bar_copy_to(priv, offset, data, size);
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}
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static void um_pci_bar_set(void *priv, unsigned int offset, u8 value, int size)
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{
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u8 *resptr = priv;
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struct um_pci_device *dev = container_of(resptr - *resptr,
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struct um_pci_device,
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resptr[0]);
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struct {
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struct virtio_pcidev_msg hdr;
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u8 data;
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} msg = {
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.hdr = {
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.op = VIRTIO_PCIDEV_OP_CFG_WRITE,
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.bar = *resptr,
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.size = size,
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.addr = offset,
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},
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.data = value,
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};
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um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0);
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}
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static const struct logic_iomem_ops um_pci_device_bar_ops = {
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.read = um_pci_bar_read,
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.write = um_pci_bar_write,
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.set = um_pci_bar_set,
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.copy_from = um_pci_bar_copy_from,
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.copy_to = um_pci_bar_copy_to,
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};
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static void __iomem *um_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where)
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{
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struct um_pci_device_reg *dev;
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unsigned int busn = bus->number;
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if (busn > 0)
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return NULL;
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/* not allowing functions for now ... */
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if (devfn % 8)
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return NULL;
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if (devfn / 8 >= ARRAY_SIZE(um_pci_devices))
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return NULL;
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dev = &um_pci_devices[devfn / 8];
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if (!dev)
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return NULL;
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return (void __iomem *)((unsigned long)dev->iomem + where);
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}
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static struct pci_ops um_pci_ops = {
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.map_bus = um_pci_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static void um_pci_rescan(void)
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{
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pci_lock_rescan_remove();
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pci_rescan_bus(bridge->bus);
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pci_unlock_rescan_remove();
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}
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|
||||
static void um_pci_irq_vq_addbuf(struct virtqueue *vq, void *buf, bool kick)
|
||||
{
|
||||
struct scatterlist sg[1];
|
||||
|
||||
sg_init_one(sg, buf, MAX_IRQ_MSG_SIZE);
|
||||
if (virtqueue_add_inbuf(vq, sg, 1, buf, GFP_ATOMIC))
|
||||
kfree(buf);
|
||||
else if (kick)
|
||||
virtqueue_kick(vq);
|
||||
}
|
||||
|
||||
static void um_pci_handle_irq_message(struct virtqueue *vq,
|
||||
struct virtio_pcidev_msg *msg)
|
||||
{
|
||||
struct virtio_device *vdev = vq->vdev;
|
||||
struct um_pci_device *dev = vdev->priv;
|
||||
|
||||
/* we should properly chain interrupts, but on ARCH=um we don't care */
|
||||
|
||||
switch (msg->op) {
|
||||
case VIRTIO_PCIDEV_OP_INT:
|
||||
generic_handle_irq(dev->irq);
|
||||
break;
|
||||
case VIRTIO_PCIDEV_OP_MSI:
|
||||
/* our MSI message is just the interrupt number */
|
||||
if (msg->size == sizeof(u32))
|
||||
generic_handle_irq(le32_to_cpup((void *)msg->data));
|
||||
else
|
||||
generic_handle_irq(le16_to_cpup((void *)msg->data));
|
||||
break;
|
||||
case VIRTIO_PCIDEV_OP_PME:
|
||||
/* nothing to do - we already woke up due to the message */
|
||||
break;
|
||||
default:
|
||||
dev_err(&vdev->dev, "unexpected virt-pci message %d\n", msg->op);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void um_pci_cmd_vq_cb(struct virtqueue *vq)
|
||||
{
|
||||
struct virtio_device *vdev = vq->vdev;
|
||||
struct um_pci_device *dev = vdev->priv;
|
||||
void *cmd;
|
||||
int len;
|
||||
|
||||
if (test_bit(UM_PCI_STAT_WAITING, &dev->status))
|
||||
return;
|
||||
|
||||
while ((cmd = virtqueue_get_buf(vq, &len))) {
|
||||
if (WARN_ON(HANDLE_IS_NO_FREE(cmd)))
|
||||
continue;
|
||||
kfree(cmd);
|
||||
}
|
||||
}
|
||||
|
||||
static void um_pci_irq_vq_cb(struct virtqueue *vq)
|
||||
{
|
||||
struct virtio_pcidev_msg *msg;
|
||||
int len;
|
||||
|
||||
while ((msg = virtqueue_get_buf(vq, &len))) {
|
||||
if (len >= sizeof(*msg))
|
||||
um_pci_handle_irq_message(vq, msg);
|
||||
|
||||
/* recycle the message buffer */
|
||||
um_pci_irq_vq_addbuf(vq, msg, true);
|
||||
}
|
||||
}
|
||||
|
||||
static int um_pci_init_vqs(struct um_pci_device *dev)
|
||||
{
|
||||
struct virtqueue *vqs[2];
|
||||
static const char *const names[2] = { "cmd", "irq" };
|
||||
vq_callback_t *cbs[2] = { um_pci_cmd_vq_cb, um_pci_irq_vq_cb };
|
||||
int err, i;
|
||||
|
||||
err = virtio_find_vqs(dev->vdev, 2, vqs, cbs, names, NULL);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
dev->cmd_vq = vqs[0];
|
||||
dev->irq_vq = vqs[1];
|
||||
|
||||
for (i = 0; i < NUM_IRQ_MSGS; i++) {
|
||||
void *msg = kzalloc(MAX_IRQ_MSG_SIZE, GFP_KERNEL);
|
||||
|
||||
if (msg)
|
||||
um_pci_irq_vq_addbuf(dev->irq_vq, msg, false);
|
||||
}
|
||||
|
||||
virtqueue_kick(dev->irq_vq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int um_pci_virtio_probe(struct virtio_device *vdev)
|
||||
{
|
||||
struct um_pci_device *dev;
|
||||
int i, free = -1;
|
||||
int err = -ENOSPC;
|
||||
|
||||
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
||||
if (!dev)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->vdev = vdev;
|
||||
vdev->priv = dev;
|
||||
|
||||
mutex_lock(&um_pci_mtx);
|
||||
for (i = 0; i < MAX_DEVICES; i++) {
|
||||
if (um_pci_devices[i].dev)
|
||||
continue;
|
||||
free = i;
|
||||
break;
|
||||
}
|
||||
|
||||
if (free < 0)
|
||||
goto error;
|
||||
|
||||
err = um_pci_init_vqs(dev);
|
||||
if (err)
|
||||
goto error;
|
||||
|
||||
dev->irq = irq_alloc_desc(numa_node_id());
|
||||
if (dev->irq < 0) {
|
||||
err = dev->irq;
|
||||
goto error;
|
||||
}
|
||||
um_pci_devices[free].dev = dev;
|
||||
vdev->priv = dev;
|
||||
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
|
||||
device_set_wakeup_enable(&vdev->dev, true);
|
||||
|
||||
um_pci_rescan();
|
||||
return 0;
|
||||
error:
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
kfree(dev);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void um_pci_virtio_remove(struct virtio_device *vdev)
|
||||
{
|
||||
struct um_pci_device *dev = vdev->priv;
|
||||
int i;
|
||||
|
||||
/* Stop all virtqueues */
|
||||
vdev->config->reset(vdev);
|
||||
vdev->config->del_vqs(vdev);
|
||||
|
||||
device_set_wakeup_enable(&vdev->dev, false);
|
||||
|
||||
mutex_lock(&um_pci_mtx);
|
||||
for (i = 0; i < MAX_DEVICES; i++) {
|
||||
if (um_pci_devices[i].dev != dev)
|
||||
continue;
|
||||
um_pci_devices[i].dev = NULL;
|
||||
irq_free_desc(dev->irq);
|
||||
}
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
|
||||
um_pci_rescan();
|
||||
|
||||
kfree(dev);
|
||||
}
|
||||
|
||||
static struct virtio_device_id id_table[] = {
|
||||
{ CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID, VIRTIO_DEV_ANY_ID },
|
||||
{ 0 },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(virtio, id_table);
|
||||
|
||||
static struct virtio_driver um_pci_virtio_driver = {
|
||||
.driver.name = "virtio-pci",
|
||||
.driver.owner = THIS_MODULE,
|
||||
.id_table = id_table,
|
||||
.probe = um_pci_virtio_probe,
|
||||
.remove = um_pci_virtio_remove,
|
||||
};
|
||||
|
||||
static struct resource virt_cfgspace_resource = {
|
||||
.name = "PCI config space",
|
||||
.start = 0xf0000000 - MAX_DEVICES * CFG_SPACE_SIZE,
|
||||
.end = 0xf0000000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static long um_pci_map_cfgspace(unsigned long offset, size_t size,
|
||||
const struct logic_iomem_ops **ops,
|
||||
void **priv)
|
||||
{
|
||||
if (WARN_ON(size > CFG_SPACE_SIZE || offset % CFG_SPACE_SIZE))
|
||||
return -EINVAL;
|
||||
|
||||
if (offset / CFG_SPACE_SIZE < MAX_DEVICES) {
|
||||
*ops = &um_pci_device_cfgspace_ops;
|
||||
*priv = &um_pci_devices[offset / CFG_SPACE_SIZE];
|
||||
return 0;
|
||||
}
|
||||
|
||||
WARN(1, "cannot map offset 0x%lx/0x%zx\n", offset, size);
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static const struct logic_iomem_region_ops um_pci_cfgspace_ops = {
|
||||
.map = um_pci_map_cfgspace,
|
||||
};
|
||||
|
||||
static struct resource virt_iomem_resource = {
|
||||
.name = "PCI iomem",
|
||||
.start = 0xf0000000,
|
||||
.end = 0xffffffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
struct um_pci_map_iomem_data {
|
||||
unsigned long offset;
|
||||
size_t size;
|
||||
const struct logic_iomem_ops **ops;
|
||||
void **priv;
|
||||
long ret;
|
||||
};
|
||||
|
||||
static int um_pci_map_iomem_walk(struct pci_dev *pdev, void *_data)
|
||||
{
|
||||
struct um_pci_map_iomem_data *data = _data;
|
||||
struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8];
|
||||
struct um_pci_device *dev;
|
||||
int i;
|
||||
|
||||
if (!reg->dev)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dev->resptr); i++) {
|
||||
struct resource *r = &pdev->resource[i];
|
||||
|
||||
if ((r->flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM)
|
||||
continue;
|
||||
|
||||
/*
|
||||
* must be the whole or part of the resource,
|
||||
* not allowed to only overlap
|
||||
*/
|
||||
if (data->offset < r->start || data->offset > r->end)
|
||||
continue;
|
||||
if (data->offset + data->size - 1 > r->end)
|
||||
continue;
|
||||
|
||||
dev = reg->dev;
|
||||
*data->ops = &um_pci_device_bar_ops;
|
||||
dev->resptr[i] = i;
|
||||
*data->priv = &dev->resptr[i];
|
||||
data->ret = data->offset - r->start;
|
||||
|
||||
/* no need to continue */
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long um_pci_map_iomem(unsigned long offset, size_t size,
|
||||
const struct logic_iomem_ops **ops,
|
||||
void **priv)
|
||||
{
|
||||
struct um_pci_map_iomem_data data = {
|
||||
/* we want the full address here */
|
||||
.offset = offset + virt_iomem_resource.start,
|
||||
.size = size,
|
||||
.ops = ops,
|
||||
.priv = priv,
|
||||
.ret = -ENOENT,
|
||||
};
|
||||
|
||||
pci_walk_bus(bridge->bus, um_pci_map_iomem_walk, &data);
|
||||
return data.ret;
|
||||
}
|
||||
|
||||
static const struct logic_iomem_region_ops um_pci_iomem_ops = {
|
||||
.map = um_pci_map_iomem,
|
||||
};
|
||||
|
||||
static void um_pci_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
|
||||
{
|
||||
/*
|
||||
* This is a very low address and not actually valid 'physical' memory
|
||||
* in UML, so we can simply map MSI(-X) vectors to there, it cannot be
|
||||
* legitimately written to by the device in any other way.
|
||||
* We use the (virtual) IRQ number here as the message to simplify the
|
||||
* code that receives the message, where for now we simply trust the
|
||||
* device to send the correct message.
|
||||
*/
|
||||
msg->address_hi = 0;
|
||||
msg->address_lo = 0xa0000;
|
||||
msg->data = data->irq;
|
||||
}
|
||||
|
||||
static struct irq_chip um_pci_msi_bottom_irq_chip = {
|
||||
.name = "UM virtio MSI",
|
||||
.irq_compose_msi_msg = um_pci_compose_msi_msg,
|
||||
};
|
||||
|
||||
static int um_pci_inner_domain_alloc(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs,
|
||||
void *args)
|
||||
{
|
||||
unsigned long bit;
|
||||
|
||||
WARN_ON(nr_irqs != 1);
|
||||
|
||||
mutex_lock(&um_pci_mtx);
|
||||
bit = find_first_zero_bit(um_pci_msi_used, MAX_MSI_VECTORS);
|
||||
if (bit >= MAX_MSI_VECTORS) {
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
set_bit(bit, um_pci_msi_used);
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
|
||||
irq_domain_set_info(domain, virq, bit, &um_pci_msi_bottom_irq_chip,
|
||||
domain->host_data, handle_simple_irq,
|
||||
NULL, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void um_pci_inner_domain_free(struct irq_domain *domain,
|
||||
unsigned int virq, unsigned int nr_irqs)
|
||||
{
|
||||
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
|
||||
|
||||
mutex_lock(&um_pci_mtx);
|
||||
|
||||
if (!test_bit(d->hwirq, um_pci_msi_used))
|
||||
pr_err("trying to free unused MSI#%lu\n", d->hwirq);
|
||||
else
|
||||
__clear_bit(d->hwirq, um_pci_msi_used);
|
||||
|
||||
mutex_unlock(&um_pci_mtx);
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops um_pci_inner_domain_ops = {
|
||||
.alloc = um_pci_inner_domain_alloc,
|
||||
.free = um_pci_inner_domain_free,
|
||||
};
|
||||
|
||||
static struct irq_chip um_pci_msi_irq_chip = {
|
||||
.name = "UM virtio PCIe MSI",
|
||||
.irq_mask = pci_msi_mask_irq,
|
||||
.irq_unmask = pci_msi_unmask_irq,
|
||||
};
|
||||
|
||||
static struct msi_domain_info um_pci_msi_domain_info = {
|
||||
.flags = MSI_FLAG_USE_DEF_DOM_OPS |
|
||||
MSI_FLAG_USE_DEF_CHIP_OPS |
|
||||
MSI_FLAG_PCI_MSIX,
|
||||
.chip = &um_pci_msi_irq_chip,
|
||||
};
|
||||
|
||||
static struct resource busn_resource = {
|
||||
.name = "PCI busn",
|
||||
.start = 0,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_BUS,
|
||||
};
|
||||
|
||||
static int um_pci_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
|
||||
{
|
||||
struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8];
|
||||
|
||||
if (WARN_ON(!reg->dev))
|
||||
return -EINVAL;
|
||||
|
||||
/* Yes, we map all pins to the same IRQ ... doesn't matter for now. */
|
||||
return reg->dev->irq;
|
||||
}
|
||||
|
||||
void *pci_root_bus_fwnode(struct pci_bus *bus)
|
||||
{
|
||||
return um_pci_fwnode;
|
||||
}
|
||||
|
||||
int um_pci_init(void)
|
||||
{
|
||||
int err, i;
|
||||
|
||||
WARN_ON(logic_iomem_add_region(&virt_cfgspace_resource,
|
||||
&um_pci_cfgspace_ops));
|
||||
WARN_ON(logic_iomem_add_region(&virt_iomem_resource,
|
||||
&um_pci_iomem_ops));
|
||||
|
||||
if (WARN(CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID < 0,
|
||||
"No virtio device ID configured for PCI - no PCI support\n"))
|
||||
return 0;
|
||||
|
||||
bridge = pci_alloc_host_bridge(0);
|
||||
if (!bridge)
|
||||
return -ENOMEM;
|
||||
|
||||
um_pci_fwnode = irq_domain_alloc_named_fwnode("um-pci");
|
||||
if (!um_pci_fwnode) {
|
||||
err = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
|
||||
um_pci_inner_domain = __irq_domain_add(um_pci_fwnode, MAX_MSI_VECTORS,
|
||||
MAX_MSI_VECTORS, 0,
|
||||
&um_pci_inner_domain_ops, NULL);
|
||||
if (!um_pci_inner_domain) {
|
||||
err = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
|
||||
um_pci_msi_domain = pci_msi_create_irq_domain(um_pci_fwnode,
|
||||
&um_pci_msi_domain_info,
|
||||
um_pci_inner_domain);
|
||||
if (!um_pci_msi_domain) {
|
||||
err = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
|
||||
pci_add_resource(&bridge->windows, &virt_iomem_resource);
|
||||
pci_add_resource(&bridge->windows, &busn_resource);
|
||||
bridge->ops = &um_pci_ops;
|
||||
bridge->map_irq = um_pci_map_irq;
|
||||
|
||||
for (i = 0; i < MAX_DEVICES; i++) {
|
||||
resource_size_t start;
|
||||
|
||||
start = virt_cfgspace_resource.start + i * CFG_SPACE_SIZE;
|
||||
um_pci_devices[i].iomem = ioremap(start, CFG_SPACE_SIZE);
|
||||
if (WARN(!um_pci_devices[i].iomem, "failed to map %d\n", i)) {
|
||||
err = -ENOMEM;
|
||||
goto free;
|
||||
}
|
||||
}
|
||||
|
||||
err = pci_host_probe(bridge);
|
||||
if (err)
|
||||
goto free;
|
||||
|
||||
err = register_virtio_driver(&um_pci_virtio_driver);
|
||||
if (err)
|
||||
goto free;
|
||||
return 0;
|
||||
free:
|
||||
if (um_pci_inner_domain)
|
||||
irq_domain_remove(um_pci_inner_domain);
|
||||
if (um_pci_fwnode)
|
||||
irq_domain_free_fwnode(um_pci_fwnode);
|
||||
pci_free_resource_list(&bridge->windows);
|
||||
pci_free_host_bridge(bridge);
|
||||
return err;
|
||||
}
|
||||
module_init(um_pci_init);
|
||||
|
||||
void um_pci_exit(void)
|
||||
{
|
||||
unregister_virtio_driver(&um_pci_virtio_driver);
|
||||
irq_domain_remove(um_pci_msi_domain);
|
||||
irq_domain_remove(um_pci_inner_domain);
|
||||
pci_free_resource_list(&bridge->windows);
|
||||
pci_free_host_bridge(bridge);
|
||||
}
|
||||
module_exit(um_pci_exit);
|
||||
|
|
@ -18,7 +18,6 @@ generic-y += mcs_spinlock.h
|
|||
generic-y += mmiowb.h
|
||||
generic-y += module.lds.h
|
||||
generic-y += param.h
|
||||
generic-y += pci.h
|
||||
generic-y += percpu.h
|
||||
generic-y += preempt.h
|
||||
generic-y += softirq_stack.h
|
||||
|
|
|
|||
|
|
@ -3,16 +3,23 @@
|
|||
#define _ASM_UM_IO_H
|
||||
#include <linux/types.h>
|
||||
|
||||
/* get emulated iomem (if desired) */
|
||||
#include <asm-generic/logic_io.h>
|
||||
|
||||
#ifndef ioremap
|
||||
#define ioremap ioremap
|
||||
static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif /* ioremap */
|
||||
|
||||
#ifndef iounmap
|
||||
#define iounmap iounmap
|
||||
static inline void iounmap(void __iomem *addr)
|
||||
{
|
||||
}
|
||||
#endif /* iounmap */
|
||||
|
||||
#include <asm-generic/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,13 @@
|
|||
|
||||
#endif
|
||||
|
||||
#define NR_IRQS 64
|
||||
#define UM_LAST_SIGNAL_IRQ 64
|
||||
/* If we have (simulated) PCI MSI, allow 64 more interrupt numbers for it */
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
#define NR_IRQS (UM_LAST_SIGNAL_IRQ + 64)
|
||||
#else
|
||||
#define NR_IRQS UM_LAST_SIGNAL_IRQ
|
||||
#endif /* CONFIG_PCI_MSI */
|
||||
|
||||
#include <asm-generic/irq.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
#include <asm-generic/msi.h>
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef __ASM_UM_PCI_H
|
||||
#define __ASM_UM_PCI_H
|
||||
#include <linux/types.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define PCIBIOS_MIN_IO 0
|
||||
#define PCIBIOS_MIN_MEM 0
|
||||
|
||||
#define pcibios_assign_all_busses() 1
|
||||
|
||||
extern int isa_dma_bridge_buggy;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
|
||||
{
|
||||
/* no legacy IRQs */
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_DOMAINS
|
||||
static inline int pci_proc_domain(struct pci_bus *bus)
|
||||
{
|
||||
/* always show the domain in /proc */
|
||||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
|
||||
/*
|
||||
* This is a bit of an annoying hack, and it assumes we only have
|
||||
* the virt-pci (if anything). Which is true, but still.
|
||||
*/
|
||||
void *pci_root_bus_fwnode(struct pci_bus *bus);
|
||||
#define pci_root_bus_fwnode pci_root_bus_fwnode
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_UM_PCI_H */
|
||||
|
|
@ -23,6 +23,7 @@ obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o
|
|||
obj-$(CONFIG_GPROF) += gprof_syms.o
|
||||
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
|
||||
obj-$(CONFIG_STACKTRACE) += stacktrace.o
|
||||
obj-$(CONFIG_GENERIC_PCI_IOMAP) += ioport.o
|
||||
|
||||
USER_OBJS := config.o
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation
|
||||
* Author: Johannes Berg <johannes@sipsolutions.net>
|
||||
*/
|
||||
#include <asm/iomap.h>
|
||||
#include <asm-generic/pci_iomap.h>
|
||||
|
||||
void __iomem *__pci_ioport_map(struct pci_dev *dev, unsigned long port,
|
||||
unsigned int nr)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
|
@ -56,7 +56,7 @@ struct irq_entry {
|
|||
|
||||
static DEFINE_SPINLOCK(irq_lock);
|
||||
static LIST_HEAD(active_fds);
|
||||
static DECLARE_BITMAP(irqs_allocated, NR_IRQS);
|
||||
static DECLARE_BITMAP(irqs_allocated, UM_LAST_SIGNAL_IRQ);
|
||||
static bool irqs_suspended;
|
||||
|
||||
static void irq_io_loop(struct irq_reg *irq, struct uml_pt_regs *regs)
|
||||
|
|
@ -419,7 +419,8 @@ unsigned int do_IRQ(int irq, struct uml_pt_regs *regs)
|
|||
|
||||
void um_free_irq(int irq, void *dev)
|
||||
{
|
||||
if (WARN(irq < 0 || irq > NR_IRQS, "freeing invalid irq %d", irq))
|
||||
if (WARN(irq < 0 || irq > UM_LAST_SIGNAL_IRQ,
|
||||
"freeing invalid irq %d", irq))
|
||||
return;
|
||||
|
||||
free_irq_by_irq_and_dev(irq, dev);
|
||||
|
|
@ -648,7 +649,7 @@ void __init init_IRQ(void)
|
|||
|
||||
irq_set_chip_and_handler(TIMER_IRQ, &alarm_irq_type, handle_edge_irq);
|
||||
|
||||
for (i = 1; i < NR_IRQS; i++)
|
||||
for (i = 1; i < UM_LAST_SIGNAL_IRQ; i++)
|
||||
irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq);
|
||||
/* Initialize EPOLL Loop */
|
||||
os_setup_epoll();
|
||||
|
|
|
|||
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2021 Intel Corporation
|
||||
* Author: Johannes Berg <johannes@sipsolutions.net>
|
||||
*/
|
||||
#ifndef _UAPI_LINUX_VIRTIO_PCIDEV_H
|
||||
#define _UAPI_LINUX_VIRTIO_PCIDEV_H
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* enum virtio_pcidev_ops - virtual PCI device operations
|
||||
* @VIRTIO_PCIDEV_OP_CFG_READ: read config space, size is 1, 2, 4 or 8;
|
||||
* the @data field should be filled in by the device (in little endian).
|
||||
* @VIRTIO_PCIDEV_OP_CFG_WRITE: write config space, size is 1, 2, 4 or 8;
|
||||
* the @data field contains the data to write (in little endian).
|
||||
* @VIRTIO_PCIDEV_OP_BAR_READ: read BAR mem/pio, size can be variable;
|
||||
* the @data field should be filled in by the device (in little endian).
|
||||
* @VIRTIO_PCIDEV_OP_BAR_WRITE: write BAR mem/pio, size can be variable;
|
||||
* the @data field contains the data to write (in little endian).
|
||||
* @VIRTIO_PCIDEV_OP_MMIO_MEMSET: memset MMIO, size is variable but
|
||||
* the @data field only has one byte (unlike @VIRTIO_PCIDEV_OP_MMIO_WRITE)
|
||||
* @VIRTIO_PCIDEV_OP_INT: legacy INTx# pin interrupt, the addr field is 1-4 for
|
||||
* the number
|
||||
* @VIRTIO_PCIDEV_OP_MSI: MSI(-X) interrupt, this message basically transports
|
||||
* the 16- or 32-bit write that would otherwise be done into memory,
|
||||
* analogous to the write messages (@VIRTIO_PCIDEV_OP_MMIO_WRITE) above
|
||||
* @VIRTIO_PCIDEV_OP_PME: Dummy message whose content is ignored (and should be
|
||||
* all zeroes) to signal the PME# pin.
|
||||
*/
|
||||
enum virtio_pcidev_ops {
|
||||
VIRTIO_PCIDEV_OP_RESERVED = 0,
|
||||
VIRTIO_PCIDEV_OP_CFG_READ,
|
||||
VIRTIO_PCIDEV_OP_CFG_WRITE,
|
||||
VIRTIO_PCIDEV_OP_MMIO_READ,
|
||||
VIRTIO_PCIDEV_OP_MMIO_WRITE,
|
||||
VIRTIO_PCIDEV_OP_MMIO_MEMSET,
|
||||
VIRTIO_PCIDEV_OP_INT,
|
||||
VIRTIO_PCIDEV_OP_MSI,
|
||||
VIRTIO_PCIDEV_OP_PME,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct virtio_pcidev_msg - virtio PCI device operation
|
||||
* @op: the operation to do
|
||||
* @bar: the bar (only with BAR read/write messages)
|
||||
* @reserved: reserved
|
||||
* @size: the size of the read/write (in bytes)
|
||||
* @addr: the address to read/write
|
||||
* @data: the data, normally @size long, but just one byte for
|
||||
* %VIRTIO_PCIDEV_OP_MMIO_MEMSET
|
||||
*
|
||||
* Note: the fields are all in native (CPU) endian, however, the
|
||||
* @data values will often be in little endian (see the ops above.)
|
||||
*/
|
||||
struct virtio_pcidev_msg {
|
||||
__u8 op;
|
||||
__u8 bar;
|
||||
__u16 reserved;
|
||||
__u32 size;
|
||||
__u64 addr;
|
||||
__u8 data[];
|
||||
};
|
||||
|
||||
#endif /* _UAPI_LINUX_VIRTIO_PCIDEV_H */
|
||||
Loading…
Reference in New Issue