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arm64: dts: ti: k3-am64-main: Add SERDES DT node
AM64 has one SERDES 10G instance. Add SERDES DT node for it. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210603142251.14563-2-kishon@ti.com
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@ -5,6 +5,17 @@
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-cadence.h>
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#include <dt-bindings/phy/phy-ti.h>
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/ {
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serdes_refclk: clock-cmnrefclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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&cbass_main {
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oc_sram: sram@70000000 {
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compatible = "mmio-sram";
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@ -18,6 +29,20 @@ atf-sram@0 {
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};
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};
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main_conf: syscon@43000000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x0 0x43000000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x43000000 0x20000>;
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serdes_ln_ctrl: mux-controller {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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@ -673,4 +698,40 @@ mailbox0_cluster7: mailbox@29070000 {
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ti,mbox-num-users = <4>;
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ti,mbox-num-fifos = <16>;
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};
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serdes_wiz0: wiz@f000000 {
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compatible = "ti,am64-wiz-10g";
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
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clock-names = "fck", "core_ref_clk", "ext_ref_clk";
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num-lanes = <1>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
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assigned-clocks = <&k3_clks 162 1>;
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assigned-clock-parents = <&k3_clks 162 5>;
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serdes0: serdes@f000000 {
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compatible = "ti,j721e-serdes-10g";
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reg = <0x0f000000 0x00010000>;
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reg-names = "torrent_phy";
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resets = <&serdes_wiz0 0>;
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reset-names = "torrent_reset";
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clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
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clock-names = "refclk", "phy_en_refclk";
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assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
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<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
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<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
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assigned-clock-parents = <&k3_clks 162 1>,
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<&k3_clks 162 1>,
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<&k3_clks 162 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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};
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};
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};
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