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Renesas ARM DT updates for v6.2

Browse source 
- DMA, SPI (MSIOF), external interrupt (INTC-EX), PWM (PWM and TPU),
     SDHI, HyperFLASH/QSPI (RPC), and serial ((H)SCIF) support for the
     R-Car V4H SoC,
   - I/O expander, eMMC, and QSPI FLASH support for the White Hawk
     development board,
   - Preparatory work to share r9a07g043.dtsi between the ARM-based
     RZ/G2UL (R9A07G043U) and the RISC-V-based RZ/Five (R9A07G043F) SoCs,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas ARM DT updates for v6.2

  - DMA, SPI (MSIOF), external interrupt (INTC-EX), PWM (PWM and TPU),
    SDHI, HyperFLASH/QSPI (RPC), and serial ((H)SCIF) support for the
    R-Car V4H SoC,
  - I/O expander, eMMC, and QSPI FLASH support for the White Hawk
    development board,
  - Preparatory work to share r9a07g043.dtsi between the ARM-based
    RZ/G2UL (R9A07G043U) and the RISC-V-based RZ/Five (R9A07G043F) SoCs,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (21 commits)
  arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
  arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
  ARM: dts: renesas: Miscellaneous whitespace fixes
  arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
  arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodes
  arm64: dts: renesas: r8a779g0: Add SCIF nodes
  arm64: dts: renesas: white-hawk-cpu: Add QSPI FLASH support
  arm64: dts: renesas: r8a779g0: Add RPC node
  arm64: dts: renesas: white-hawk-cpu: Add eMMC support
  arm64: dts: renesas: r8a779g0: Add SDHI node
  arm64: dts: renesas: rzg2l: Drop WDT2 nodes
  arm64: dts: renesas: r8a779g0: Add TPU device node
  arm64: dts: renesas: r8a779g0: Add PWM device nodes
  arm64: dts: renesas: r8a779g0: Fix HSCIF0 "brg_int" clock
  arm64: dts: renesas: condor-common: Add missing bootargs
  arm64: dts: renesas: white-hawk-cpu: Add PCA9654 I/O Expander
  arm64: dts: renesas: r8a779g0: Add INTC-EX node
  arm64: dts: renesas: r8a779g0: Add MSIOF nodes
  arm64: dts: renesas: r8a779g0: Add DMA support
  arm64: dts: renesas: rzg2ul-smarc: Move spi1 pinmux to carrier board DTSI
  ...

Link: https://lore.kernel.org/r/cover.1667558740.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-11-14 14:55:43 +01:00
commit 6902029ec8
20 changed files with 830 additions and 316 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/boot/dts/r8a7742.dtsi
View file

@ -1298,7 +1298,7 @@ ssi0: ssi-0 {
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";

2
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -1252,7 +1252,7 @@ ssi0: ssi-0 {
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";

2
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -1365,7 +1365,7 @@ ssi0: ssi-0 {
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";

2
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -1111,7 +1111,7 @@ ssi0: ssi-0 {
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>,
<&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";

10
arch/arm/boot/dts/r9a06g032.dtsi
View file

@ -199,7 +199,7 @@ uart3: serial@50000000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -212,7 +212,7 @@ uart4: serial@50001000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -225,7 +225,7 @@ uart5: serial@50002000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -238,7 +238,7 @@ uart6: serial@50003000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -251,7 +251,7 @@ uart7: serial@50004000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
dma-names = "rx", "tx";
status = "disabled";
};

1
arch/arm64/boot/dts/renesas/condor-common.dtsi
View file

@ -21,6 +21,7 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
d1_8v: regulator-2 {

24
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View file

@ -656,7 +656,7 @@ channel7 {
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
@ -704,7 +704,7 @@ avb0: ethernet@e6800000 {
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6810000 0 0x800>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@ -752,7 +752,7 @@ avb1: ethernet@e6810000 {
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
@ -800,7 +800,7 @@ avb2: ethernet@e6820000 {
avb3: ethernet@e6830000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6830000 0 0x1000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
@ -848,7 +848,7 @@ avb3: ethernet@e6830000 {
avb4: ethernet@e6840000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6840000 0 0x1000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
@ -896,7 +896,7 @@ avb4: ethernet@e6840000 {
avb5: ethernet@e6850000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
"renesas,etheravb-rcar-gen4";
reg = <0 0xe6850000 0 0x1000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
@ -1019,7 +1019,7 @@ tpu: pwm@e6e80000 {
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
@ -1034,7 +1034,7 @@ msiof0: spi@e6e90000 {
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
@ -1049,7 +1049,7 @@ msiof1: spi@e6ea0000 {
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
@ -1064,7 +1064,7 @@ msiof2: spi@e6c00000 {
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
@ -1079,7 +1079,7 @@ msiof3: spi@e6c10000 {
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
@ -1094,7 +1094,7 @@ msiof4: spi@e6c20000 {
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;

85
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
View file

@ -96,6 +96,24 @@ memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb0 {
@ -135,6 +153,17 @@ &i2c0 {
status = "okay";
clock-frequency = <400000>;
io_expander_a: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
eeprom@50 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "cpu-board";
@ -143,6 +172,23 @@ eeprom@50 {
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
@ -180,12 +226,51 @@ keys_pins: keys {
bias-pull-up;
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot@0 {
reg = <0x0 0x1200000>;
read-only;
};
user@1200000 {
reg = <0x1200000 0x2e00000>;
};
};
};
};
&scif_clk {
clock-frequency = <24000000>;
};

470
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
View file

@ -235,12 +235,31 @@ sysc: system-controller@e6180000 {
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 611>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 611>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779g0",
"renesas,rcar-gen4-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
dmas = <&dmac0 0x91>, <&dmac0 0x90>,
<&dmac1 0x91>, <&dmac1 0x90>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
i2c-scl-internal-delay-ns = <110>;
@ -255,6 +274,9 @@ i2c1: i2c@e6508000 {
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
dmas = <&dmac0 0x93>, <&dmac0 0x92>,
<&dmac1 0x93>, <&dmac1 0x92>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
i2c-scl-internal-delay-ns = <110>;
@ -269,6 +291,9 @@ i2c2: i2c@e6510000 {
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
dmas = <&dmac0 0x95>, <&dmac0 0x94>,
<&dmac1 0x95>, <&dmac1 0x94>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
i2c-scl-internal-delay-ns = <110>;
@ -283,6 +308,9 @@ i2c3: i2c@e66d0000 {
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>,
<&dmac1 0x97>, <&dmac1 0x96>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
i2c-scl-internal-delay-ns = <110>;
@ -297,6 +325,9 @@ i2c4: i2c@e66d8000 {
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
dma-names = "tx", "rx", "tx", "rx";
dmas = <&dmac0 0x99>, <&dmac0 0x98>,
<&dmac1 0x99>, <&dmac1 0x98>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 522>;
i2c-scl-internal-delay-ns = <110>;
@ -311,6 +342,9 @@ i2c5: i2c@e66e0000 {
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 523>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
<&dmac1 0x9b>, <&dmac1 0x9a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 523>;
i2c-scl-internal-delay-ns = <110>;
@ -321,19 +355,72 @@ i2c5: i2c@e66e0000 {
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779g0",
"renesas,rcar-gen4-hscif",
"renesas,hscif";
reg = <0 0xe6540000 0 96>;
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
<&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x31>, <&dmac0 0x30>,
<&dmac1 0x31>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
status = "disabled";
};
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a779g0",
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x33>, <&dmac0 0x32>,
<&dmac1 0x33>, <&dmac1 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 515>;
status = "disabled";
};
hscif2: serial@e6560000 {
compatible = "renesas,hscif-r8a779g0",
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
<&dmac1 0x35>, <&dmac1 0x34>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 516>;
status = "disabled";
};
hscif3: serial@e66a0000 {
compatible = "renesas,hscif-r8a779g0",
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>,
<&dmac1 0x37>, <&dmac1 0x36>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779g0",
"renesas,etheravb-rcar-gen4";
@ -475,6 +562,381 @@ avb2: ethernet@e6820000 {
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm7: pwm@e6e37000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e37000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm8: pwm@e6e38000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e38000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
pwm9: pwm@e6e39000 {
compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
reg = <0 0xe6e39000 0 0x10>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 628>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 628>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779g0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x51>, <&dmac0 0x50>,
<&dmac1 0x51>, <&dmac1 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a779g0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x53>, <&dmac0 0x52>,
<&dmac1 0x53>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a779g0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>,
<&dmac1 0x57>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a779g0",
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
<&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
<&dmac1 0x59>, <&dmac1 0x58>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 705>;
status = "disabled";
};
tpu: pwm@e6e80000 {
compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
reg = <0 0xe6e80000 0 0x148>;
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 718>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 718>;
#pwm-cells = <3>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
dmas = <&dmac0 0x41>, <&dmac0 0x40>,
<&dmac1 0x41>, <&dmac1 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 618>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
dmas = <&dmac0 0x43>, <&dmac0 0x42>,
<&dmac1 0x43>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 619>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>,
<&dmac1 0x45>, <&dmac1 0x44>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 620>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>,
<&dmac1 0x47>, <&dmac1 0x46>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 621>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
dmas = <&dmac0 0x49>, <&dmac0 0x48>,
<&dmac1 0x49>, <&dmac1 0x48>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 622>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779g0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
<&dmac1 0x4b>, <&dmac1 0x4a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 623>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac0: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779g0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7350000 0 0x1000>,
<0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 709>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac1: dma-controller@e7351000 {
compatible = "renesas,dmac-r8a779g0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7351000 0 0x1000>,
<0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 710>;
clock-names = "fck";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <16>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779g0",
"renesas,rcar-gen4-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>,
<&cpg CPG_CORE R8A779G0_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
status = "disabled";
};
rpc: spi@ee200000 {
compatible = "renesas,r8a779g0-rpc-if",
"renesas,rcar-gen4-rpc-if";
reg = <0 0xee200000 0 0x200>,
<0 0x08000000 0 0x04000000>,
<0 0xee208000 0 0x100>;
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;

362
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View file

@ -1,11 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SoC
* Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g043-cpg.h>
/ {
@ -69,36 +68,8 @@ opp-1000000000 {
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -107,10 +78,10 @@ ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
@ -128,10 +99,10 @@ ssi1: ssi@1004a000 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
@ -149,10 +120,10 @@ ssi2: ssi@1004a400 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
@ -170,10 +141,10 @@ ssi3: ssi@1004a800 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
@ -190,9 +161,9 @@ ssi3: ssi@1004a800 {
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
@ -208,9 +179,9 @@ spi0: spi@1004ac00 {
spi1: spi@1004b000 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
@ -226,9 +197,9 @@ spi1: spi@1004b000 {
spi2: spi@1004b400 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
@ -245,12 +216,12 @@ scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
@ -264,12 +235,12 @@ scif1: serial@1004bc00 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
@ -283,12 +254,12 @@ scif2: serial@1004c000 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
@ -302,12 +273,12 @@ scif3: serial@1004c400 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
@ -321,12 +292,12 @@ scif4: serial@1004c800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
@ -339,10 +310,10 @@ scif4: serial@1004c800 {
sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
clock-names = "fck";
@ -354,10 +325,10 @@ sci0: serial@1004d000 {
sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
clock-names = "fck";
@ -369,14 +340,14 @@ sci1: serial@1004d400 {
canfd: can@10050000 {
compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
@ -405,14 +376,14 @@ i2c0: i2c@10058000 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
@ -427,14 +398,14 @@ i2c1: i2c@10058400 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
@ -449,14 +420,14 @@ i2c2: i2c@10058800 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
@ -471,14 +442,14 @@ i2c3: i2c@10058c00 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
@ -491,7 +462,7 @@ i2c3: i2c@10058c00 {
adc: adc@10059000 {
compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G043_ADC_PCLK>;
clock-names = "adclk", "pclk";
@ -551,12 +522,6 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@ -578,23 +543,23 @@ dmac: dma-controller@11820000 {
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@ -609,22 +574,12 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
@ -639,8 +594,8 @@ sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
@ -655,9 +610,9 @@ eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
@ -675,9 +630,9 @@ eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
@ -705,7 +660,7 @@ phyrst: usbphy-ctrl@11c40000 {
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@ -719,7 +674,7 @@ ohci0: usb@11c50000 {
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@ -733,7 +688,7 @@ ohci1: usb@11c70000 {
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@ -748,7 +703,7 @@ ehci0: usb@11c50100 {
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@ -764,7 +719,7 @@ usb2_phy0: usb-phy@11c50200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
@ -777,7 +732,7 @@ usb2_phy1: usb-phy@11c70200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
@ -790,10 +745,10 @@ hsusb: usb@11c60000 {
compatible = "renesas,usbhs-r9a07g043",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>,
<SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
@ -812,34 +767,19 @@ wdt0: watchdog@12800800 {
clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g043-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
power-domains = <&cpg>;
@ -850,7 +790,7 @@ ostm1: timer@12801400 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
power-domains = <&cpg>;
@ -861,7 +801,7 @@ ostm2: timer@12801800 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
power-domains = <&cpg>;
@ -899,12 +839,4 @@ target: trip-point {
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

72
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi Normal file
View file

@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include "r9a07g043.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
compatible = "cache";
cache-unified;
cache-size = <0x40000>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
&soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@11900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x11900000 0 0x40000>,
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
};
&sysc {
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
};

2
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
View file

@ -17,7 +17,7 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
#include "r9a07g043.dtsi"
#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"

15
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View file

@ -994,21 +994,6 @@ wdt1: watchdog@12800c00 {
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G044_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g044-ostm",
"renesas,ostm";

30
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
View file

@ -6,7 +6,37 @@
*/
/dts-v1/;
/*
* DIP-Switch SW1 setting on SoM
* 1 : High; 0: Low
* SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
* SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
* SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
* SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
* Please change below macros according to SW1 setting
*/
#define SW_SD0_DEV_SEL 1
#define SW_SCIF_CAN 0
#if (SW_SCIF_CAN)
/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
#define SW_RSPI_CAN 0
#else
/* Please set SW_RSPI_CAN. Default value is 1 */
#define SW_RSPI_CAN 1
#endif
#if (SW_SCIF_CAN && SW_RSPI_CAN)
#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
#endif
/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
#include "r9a07g044c2.dtsi"
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc.dtsi"
/ {

15
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View file

@ -1000,21 +1000,6 @@ wdt1: watchdog@12800c00 {
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g054-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G054_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G054_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g054-ostm",
"renesas,ostm";

5
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View file

@ -351,8 +351,3 @@ &wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

5
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
View file

@ -276,8 +276,3 @@ &wdt1 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

28
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View file

@ -8,37 +8,9 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/*
* DIP-Switch SW1 setting on SoM
* 1 : High; 0: Low
* SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
* SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
* SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
* SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
* Please change below macros according to SW1 setting
*/
#define SW_SD0_DEV_SEL 1
#define SW_SCIF_CAN 0
#if (SW_SCIF_CAN)
/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
#define SW_RSPI_CAN 0
#else
/* Please set SW_RSPI_CAN. Default value is 1 */
#define SW_RSPI_CAN 1
#endif
#if (SW_SCIF_CAN && SW_RSPI_CAN)
#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
#endif
#include "rzg2lc-smarc-som.dtsi"
#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
#define PMOD1_SER0 1
/ {
aliases {

7
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
View file

@ -99,6 +99,13 @@ sound_clk_pins: sound_clk {
input-enable;
};
spi1_pins: spi1 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
<RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
<RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
<RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
};
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */
<RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */

7
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
View file

@ -221,13 +221,6 @@ sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
spi1_pins: rspi1 {
pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
<RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
<RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
<RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
};
};
#if (SW_SW0_DEV_SEL)