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x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains
commit 75d1cc0e05
upstream.
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a
system, it is not required for software to flush the page from all CPU
caches in the system prior to changing the value of the C-bit for the
page. So check that bit before flushing the cache.
[ bp: Massage commit message. ]
Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhukhan@oracle.com
Signed-off-by: Liam Merwick <liam.merwick@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -1967,7 +1967,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
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/*
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* Before changing the encryption attribute, we need to flush caches.
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*/
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cpa_flush(&cpa, 1);
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cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
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ret = __change_page_attr_set_clr(&cpa, 1);
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