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usb: phy: omap-usb3: fix dpll clock index
Correction of the omap_usb3_dpll_params array when the sys_clk_rate is 20MHz. Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com> Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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@ -71,9 +71,9 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
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{1250, 5, 4, 20, 0}, /* 12 MHz */
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{3125, 20, 4, 20, 0}, /* 16.8 MHz */
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{1172, 8, 4, 20, 65537}, /* 19.2 MHz */
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{1000, 7, 4, 10, 0}, /* 20 MHz */
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{1250, 12, 4, 20, 0}, /* 26 MHz */
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{3125, 47, 4, 20, 92843}, /* 38.4 MHz */
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{1000, 7, 4, 10, 0}, /* 20 MHz */
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};
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